SMSC LAN9420, LAN9420i 4.4.3MAC Address Low Register (ADDRL), BITS, TYPE, DEFAULT, DESCRIPTION, ADDRL, ADDRH, Physical Address [31:0], ORDER OF RECEPTION ON ETHERNET

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

4.4.3MAC Address Low Register (ADDRL)

Offset: 0088h Size: 32 bits

This register contains the lower 32 bits of the physical address of the MAC, where ADDRL[7:0] is the first octet of the Ethernet frame.

BITS	DESCRIPTION	TYPE	DEFAULT
31:0	Physical Address [31:0]	R/W	32‘hF
	This field contains the lower 32 bits (32:0) of the Physical Address of this
	MAC device.

Table 4.6 below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the Ethernet physical address.

	Table 4.6 ADDRL, ADDRH Byte Ordering
ADDRL, ADDRH		ORDER OF RECEPTION ON ETHERNET
ADDRL[7:0]		1st
ADDRL[15:8]		2nd
ADDRL[23:16]		3rd
ADDRL[31:24]		4th
ADDRH[7:0]		5th
ADDRH[15:8]		6th

As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and ADDRH registers would be programmed as shown in Figure 4.2. The values required to automatically load this configuration from the EEPROM are shown in Section 3.3.5.1, "EEPROM Format," on page 31.

31	24 23		16 15		8	7	0
xx		xx		0xBC			0x9A
			ADDRH
31	24 23		16 15		8	7	0
0x78		0x56		0x34			0x12

ADDRL

Figure 4.2 Example ADDRL, ADDRH Address Ordering

Revision 1.22 (09-25-08)	124	SMSC LAN9420/LAN9420i
	DATASHEET