Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

„When the memory buffer ends before the frame ends for the current transfer

„When the controller completes the reception of a frame and the current receive descriptor has been closed

„When the receive process is suspended because of a Host-owned buffer (RDES0[31]=0) and a new frame is being received

„When receive poll demand is issued

3.4.7Suspend State Behavior

The following sections detail the suspend state behavior of the transmit and receive engines.

3.4.7.1Transmit Engine

The Transmit Engine enters the suspended state when either of these conditions occurs:

„The DMA controller detects a descriptor owned by the Host system (TDES0[31]=0). To resume, the driver must give the descriptor ownership to the DMA controller and then issue a poll demand command.

„A DMA transmission was aborted due to a local error.

In both of these cases the abnormal interrupt summary (AIS bit in the DMAC_STATUS register) and the transmit interrupt (TI bit in the DMAC_STATUS register) are set and the appropriate status bit in TDES0 is set. The position in the transmit list is retained. The retained position is that of the descriptor following the descriptor that was last closed.

Note: The DMA controller does not automatically poll the transmit descriptor list. The driver must explicitly issue a transmit poll demand after rectifying the suspension cause.

3.4.7.2Receive Engine

The Receive Engine enters the suspended state when a receive buffer is unavailable. If a frame arrives when the receiver is in the suspended state, the receive engine re-fetches the descriptor and, if now owned by the DMA controller, reenters the running state and starts frame reception. Receive polling resumes from the last list position. The DMA controller generates a Receive Buffer Unavailable interrupt (RU bit in the DMAC_STATUS register) only once - when entering the suspended state from the running state. In the suspended state, if a new frame is received and a descriptor is still not available, the frame is discarded. Only in the suspended state does the controller respond to a Receive Poll Demand (for example, a buffer is available before the next incoming frame) and enter the running state.

3.4.8Stopping Transmission and Reception

The receive and transmit processes and paths are independent of each other. One does not need to be stopped as a result of stopping the other. However, the sequence of operations required to stop elements in the receive path must be explicitly followed, in order to preclude unexpected results and untoward operation.

In order to stop the transmission, the TX DMAC should be stopped before the MAC’s transmitter (Clear bit 13 (ST) of DMAC_CONTROL to stop TX DMA, then clear bit 3 (TXEN) of MAC_CR to turn the transmitter off).

In order to stop reception, the MAC’s receiver should be stopped prior to stopping the RX DMAC (Clear bit 2 (RXEN) of MAC_CR to turn the receiver off, then clear bit 1 (SR) of DMAC_CONTROL to stop RX DMA). Performing these steps in the reverse order will result in RX DMA not stopping (DMAC_STATUS will continue to show the Receive Process State (RS) as Running and Receive Process Stopped (RPS) does not assert).

SMSC LAN9420/LAN9420i

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Revision 1.22 (09-25-08)

 

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