Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

4.2.8Bus Master Bridge Configuration Register (BUS_CFG)

 

Offset:

00DCh

Size:

32 bits

 

 

This register determines the bus arbitration characteristics for the RX and TX DMA engines.

 

 

 

 

 

 

 

BITS

 

DESCRIPTION

 

 

TYPE

DEFAULT

 

 

 

 

 

 

 

31:28

RESERVED

 

 

 

RO

-

 

 

 

 

 

 

 

27

RESERVED

 

 

 

R/W

0b

 

 

 

 

 

26:25

RX/TX Arbitration Priority Select (CSR_RXTXWEIGHT)

 

R/W

00b

 

This field selects the arbitration priority ratio for receive and transmit DMA

 

 

 

operations. This field has no effect unless the BAR bit in the BUS_MODE

 

 

 

DCSR is cleared.

 

 

 

 

 

Setting

Priority Ratio (RX:TX)

 

 

 

 

 

------------------------------------------------

 

 

 

 

 

00b

1:1

 

 

 

 

 

01b

2:1

 

 

 

 

 

10b

3:1

 

 

 

 

 

11b

4:1

 

 

 

 

 

 

 

 

 

 

 

24:0

RESERVED

 

 

 

RO

-

 

 

 

 

 

 

 

Revision 1.22 (09-25-08)

96

SMSC LAN9420/LAN9420i

 

DATASHEET