SMSC LAN9420, LAN9420i 5.8EEPROM Timing, MIN, TYP, MAX, UNITS, SYMBOL, DESCRIPTION, Figure 5.4 EEPROM Timing, Table 5.12 EEPROM Timing Values

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

5.8EEPROM Timing

The following specifies the EEPROM timing requirements for LAN9420/LAN9420i:

					tcsl
	EECS
	tckcyc			tcklcsl
	tcshckh tckh tckl
	EECLK
	tdvckh	tckhdis		tckldis
	EEDO
	tdsckh	tdhckh
	EEDI
	tcshdv			tdhcsl
EEDI (VERIFY)
	Figure 5.4 EEPROM Timing
	Table 5.12 EEPROM Timing Values
SYMBOL	DESCRIPTION		MIN	TYP	MAX	UNITS
tckcyc	EECLK Cycle time		1110		1130	ns
tckh	EECLK High time		550		570	ns
tckl	EECLK Low time		550		570	ns
tcshckh	EECS high before rising edge of EECLK		1070			ns
tcklcsl	EECLK falling edge to EECS low		30			ns
tdvckh	EEDIO valid before rising edge of EECLK		550			ns
	(OUTPUT)
tckhdis	EEDIO disable after rising edge EECLK		550			ns
	(OUTPUT)
tdsckh	EEDIO setup to rising edge of EECLK (INPUT)		90			ns
tdhckh	EEDIO hold after rising edge of EECLK		0			ns
	(INPUT)
tckldis	EECLK low to data disable (OUTPUT)		580			ns
tcshdv	EEDIO valid after EECS high (VERIFY)				600	ns
tdhcsl	EEDIO hold after EECS low (VERIFY)		0			ns
tcsl	EECS low		1070			ns

SMSC LAN9420/LAN9420i	165	Revision 1.22 (09-25-08)
	DATASHEET