Datasheet
b.The software application must wait for all pending DMA transactions to complete. Upon completion, no further transactions are permitted.
2.The ENERGYON event must be enabled as a PHY interrupt source. This is done by setting the INT7 bit in the PHY’s Interrupt Source Flag register.
3.The PHY must be enabled for the energy detect power down mode This is done by clearing the EDPWRDOWN bit in the PHY’s Mode Control/Status register. Enabling the energy detect power- down mode places the PHY in a reduced power state. In this mode of operation the PHY is not capable of receiving or transmitting Ethernet data. In this state the PHY will assert its internal interrupt if it detects Ethernet activity. Refer to Section 3.6.8.2, "Energy Detect
4.Bit 0 of the Wakeup Status (WUPS[0]) in the Power Management Control Register (PMT_CTRL) must be cleared since a set bit will cause the immediate assertion of wake event when ED_EN is set. The WUPS[0] bit will not clear if the internal PHY interrupt is asserted.
5.Set the
6.Set the PME Enable (PME_EN) bit in the PCI Power Management Control and Status Register (PCI_PMCSR). Note that PME_EN must be set before entering the D3 state. If this bit is not set, the internal PHY will be reset and placed in the General
7.If the device is to be placed in the D3 state, set the Power Management State (PM_STATE) field of the PCI Power Management Control and Status Register (PCI_PMCSR) to 11b (‘D3’ state). The
device will enter D3HOT. Device behavior in this state is described in Section 3.7.4.4, "The D3HOT State," on page 77.
On detection of Ethernet activity (energy), the device will assert the nPME signal. The nPME signal will remain asserted until the PME Enable (PME_EN) and/or the PME Status (PME_STATUS) bits are cleared by the Host.
Revision 1.22 | 82 | SMSC LAN9420/LAN9420i |
| DATASHEET |
|