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Datasheet
3.7.5ResetsThe LAN9420/LAN9420i device employs the following resets:
PCInRST: This is the
D3 Transition Reset (D3RST): This reset occurs when transitioning from the D3HOT to D0U states.
Software Reset (SRST): This reset is initiated by setting the Software Reset (SRST) bit in the Bus Mode Register (BUS_MODE). Software Reset does not clear control register bits marked as NASR.
PHY Reset via PMT_CTRL (PHY_RST): This reset is asserted by setting the PHY Reset (PHY_RST) in the Power Management Control Register (PMT_CTRL). Refer to section Section 3.6.9.1, "PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)," on page 73 for more information.
PHY Soft Reset (PHY_SRST): This reset is asserted by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register. Refer to section Section 3.6.9.2, "PHY Soft Reset via PHY Basic Control Register bit 15 (PHY Reg. 0.15)," on page 73 for more information.
The reset map in Table 3.22 shows the conditions under which various modules within LAN9420/LAN9420i are reset.
Table 3.22 Reset MapBLOCK | POR | PCInRST | D3RST | SRST | PHY_RST | PHY_SRST |
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PCI PME Logic | X |
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PHY | X | X |
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EEPROM Load | X | X |
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PCI Configuration | X | X | X |
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Registers |
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(except PME registers) |
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MAC | X | X | X | X |
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TX/RX DMACS | X | X | X | X |
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SCSR | X | X | X | X |
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(Note 3.7)
Note 3.6 PME logic is reset by PCInRST if LAN9420/LAN9420i is not configured to support D3COLD wake; PME logic is not reset by PCInRST if LAN9420/LAN9420i is configured to support D3COLD wake.
Note 3.7 Software Reset does not clear control register bits marked as NASR.
Note 3.8 If PHY was reset on entry to the D3HOT, it will be reset when exiting the D3HOT. If the PHY was not reset on entry to the D3HOT, it will not be reset when exiting D3HOT.
Note 3.9 The Subsystem Vendor ID (SSVID) Subsystem Device ID (SSID) registers (optionally loaded from the EEPROM) are not reset during this transition.
SMSC LAN9420/LAN9420i | 79 | Revision 1.22 |
| DATASHEET |
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