
Datasheet
3.2.4PCI Target InterfaceThe PCI target interface implements the address spaces listed in Table 3.1.
|
| Table 3.1 PCI Address Spaces |
|
|
|
SPACE | SIZE | RESOURCE |
|
|
|
Configuration | 256 bytes | PCI standard and |
|
|
|
BAR0...BAR2 |
| RESERVED |
|
|
|
BAR3 | 1 KB | Control and Status Registers |
|
|
|
BAR4 | 256B | Control and Status Registers (I/O area) |
|
|
|
BAR5 |
| RESERVED |
|
|
|
Expansion ROM | - | RESERVED |
|
|
|
The PCI Configuration space is used to identify PCI Devices, configure memory ranges, and manage interrupts. The Host initializes and configures the PCI Device during a
The PCI Target Interface supports
3.2.4.1PCI Configuration Space Registers
PCI Configuration Space Registers include the standard PCI header registers and PCIB extensions to implement power management control/status registers. See Section 4.6, "PCI Configuration Space CSR (CONFIG CSR)," on page 149 for further details. These registers exist in the configuration space.
3.2.4.2Control and Status Registers (CSR)
The PCI Target Interface allows PCI bus masters to directly access the LAN9420/LAN9420i Control and Status registers via memory or I/O operations. Each set of operations has an associated address range that defines it as follows:
The
The I/O address range is mapped in BAR4.
3.2.4.2.1CSR ENDIANNESS
The
Revision 1.22 | 26 | SMSC LAN9420/LAN9420i |
| DATASHEET |
|