Datasheet
D3HOT to D0U (T8): This transition occurs when PCInRST is asserted while in the D3HOT state (PCInRST=1 to 0, PM_STATE=11b, VAUXDET=X, PWRGOOD=1). Refer to Section 3.7.5, "Resets," on page 79 to for more information on this reset.
D3HOT to G3 (T12): This transition occurs when all power supplies are turned off (PCInRST=X, PM_STATE=XXb, VAUXDET=1 to 0, PWRGOOD=1 to 0). For example, total power failure.
3.7.4.5The D3COLD State
LAN9420/LAN9420i’s behavior in this state is dependant on the status of VAUXDET. When
VAUXDET=0, LAN9420/LAN9420i is powered from the system’s +3.3V supply; wake from D3COLD is disabled and the PCI +3.3V power supply is off. Since VAUXDET=0, the device is powered from the system’s +3.3V power supply and LAN9420/LAN9420i loses all power and context (to LAN9420/LAN9420i, this appears identical to the G3 state).
When VAUXDET=1, LAN9420/LAN9420i is powered from the auxiliary power supply and the auxiliary 3.3Vaux supply remains operational. The device is isolated from the PCI bus and ignores all PCI accesses, as well as PCInRST. If the PME Enable (PME_EN) bit in the PCI Power Management Control and Status Register (PCI_PMCSR) is set, it is assumed that the device is configured to detect
a wake event from D3COLD. In this state the PCI 3.3Vaux power is on, but normal Ethernet receive and transmit operation is disabled. In D3COLD power is reduced by disabling the internal PLL and derivative clocks.
3.7.4.5.1POWER MANAGEMENT EVENTS IN D3COLD
If configured to do so, the device is capable of detecting MAC (WOL, Magic Packet) and PHY (link status change) wake events and is capable of asserting nPME as a result of detection. In order to
generate nPME in the D3COLD state, LAN9420/LAN9420i must be powered from the 3.3Vaux power supply.
3.7.4.5.2EXITING THE D3COLD STATE
The device will exit the D3COLD state under the following conditions. State transitions are illustrated in Figure 3.28 on page 75.
D3COLD to D0U (T9): This transition occurs when the +3.3V power supply is turned on. If VAUXDET = 1, this means that the 3.3Vaux supply was active and PCI power is now turned on (PCInRST=1 to 0, PM_STATE=11b, VAUXDET=1, PWRGOOD=0 to 1). In this case the entire device is reset, with the exception of the PCI PME context, which is preserved. The internal PHY is reset and is configured for all capable operation with auto negotiation enabled.
If VAUXDET = 0, the device is seeing power for the first time and the internal
D3COLD to G3 (T12): This transition occurs when all power supplies are turned off (PCInRST=X, PM_STATE=XXb, VAUXDET=1 to 0, PWRGOOD=1 to 0). For example, total power failure.
Revision 1.22 | 78 | SMSC LAN9420/LAN9420i |
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