Datasheet
{DSAP, SSAP, CTRL, | {OUI[15:0], PID[15:0]} |
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OUI[23:16]} |
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| 8 | V L | S | S |
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| N | N |
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DST SRC | 1 | L3 Packet | ||||
0 | I e | A | A | C | ||
| 0 | D n | P | P |
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| 0 | 1 |
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0 1 2 3 4 5 6
Calculate Checksum
Figure 3.23 Ethernet Frame with VLAN Tag and SNAP Header{DSAP, SSAP, CTRL, | {OUI[15:0], PID[15:0]} |
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| OUI[23:16]} |
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| 8 | V | 8 | V L | S | S |
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| N | N |
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DST SRC | 1 | I | 1 | I e | A | A | L3 Packet | C |
| 0 | D | 0 | D n | P | P |
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| 0 |
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| 0 | 1 |
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0 1 2 4 5 6 7 8
Calculate Checksum
Figure 3.24 Ethernet Frame with multiple VLAN Tags and SNAP HeaderThe RXCOE supports a maximum of two VLAN tags. If there are more than two VLAN tags, the VLAN protocol identifier for the third tag is treated as an Ethernet type field. The checksum calculation will begin immediately after the type field.
The RXCOE resides in the RX path within the MAC. As the RXCOE receives an Ethernet frame it calculates the
Setting the RX_COE_EN bit in the Checksum Offload Engine Control Register (COE_CR) enables the RXCOE, while the RX_COE_MODE bit selects the operating mode. When the RXCOE is disabled, the received data is simply passed through the RXCOE unmodified.
Note: Software applications must stop the receiver and flush the RX data path before changing the state of the RX_COE_EN or RX_COE_MODE bits.
Note: When the RXCOE is enabled, automatic pad stripping must be disabled (PADSTR bit of the MAC Control Register (MAC_CR)) and vice versa. These functions cannot be enabled simultaneously.
Revision 1.22 | 62 | SMSC LAN9420/LAN9420i |
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