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SMSC LAN9420, LAN9420i ERAL (Erase All):, Figure 3.9 EEPROM ERAL Cycle, Figure 3.8 EEPROM ERASE Cycle

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Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

tCSL

EECS

EECLK

EEDIO (OUTPUT)

EEDIO (INPUT)

Figure 3.8 EEPROM ERASE Cycle

ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms.

tCSL

EECS

EECLK

EEDIO (OUTPUT)

EEDIO (INPUT)

Figure 3.9 EEPROM ERAL Cycle

Revision 1.22 (09-25-08)	34	SMSC LAN9420/LAN9420i
	DATASHEET

Contents

LAN9420/LAN9420i Single-ChipEthernet Controller with HP Auto-MDIXSupport and PCI Interface Highlights Target Applications Key Benefits ORDER NUMBERS: Table of Contents Page Page Page Page List of Figures List of Tables Page Chapter 1 Introduction 1.1Block Diagrams LAN9420/LAN9420i 1.2General Description 1.3PCI Bridge 1.4DMA Controller 1.5Ethernet MAC 1.6Ethernet PHY 1.7System Control Block 1.8Control and Status Registers (CSR) Chapter 2 Pin Description and Configuration TOP VIEW 2.1Pin List Table 2.2 EEPROM EEPROM Data: General Purpose Output 3: This pin can also function TX_EN Signal Monitor: TX_CLK Signal Monitor: Table 2.3 GPIO and LED Pins General Purpose I/O data 0: This general-purposepin is nLED1 (Speed Indicator): General Purpose I/O data 1: This general-purposepin is nLED2 (Link & Activity Indicator): This pin can also Table 2.5 PLL and Ethernet PHY Pins Crystal Input: Crystal Output: Ethernet Transmit Data Out Negative: The transmit Ethernet Transmit Data Out Positive: The transmit Table 2.6 Power and Ground Pins +3.3V Analog Power Supply +1.8V PLL Power Supply: +1.8V Transmitter Power Supply: This pin must be +3.3V Master Bias Power Supply Table 2.8 128-VTQFPPackage Pin Assignments PIN PIN NAME 2.2Buffer Types Chapter 3 Functional Description 3.1Functional Overview 3.2PCI Bridge (PCIB) 3.2.1PCI Bridge (PCIB) Block Diagram PCI Bridge (PCIB) Figure 3.1 PCI Bridge Block Diagram 3.2.3.1PCI Master Transaction Errors 3.2.4.1PCI Configuration Space Registers 3.2.4.2Control and Status Registers (CSR) 3.2.4.3PCI Target Interface Transaction Errors 3.2.4.4PCI Discard Timer 3.3System Control Block (SCB) Figure 3.6 Interrupt Controller Block Diagram 3.3.2Wake Event Detection Logic 3.3.3General Purpose Timer (GPT) 3.3.5.1EEPROM Format 3.3.5.2MAC Address, Subsystem ID, and Subsystem Vendor ID Auto-Load 3.3.5.3EEPROM Host Operations EEPROM Write EEPROM Read Figure 3.7 EEPROM Access Flow Diagram 3.3.5.3.1SUPPORTED EEPROM OPERATIONS ERASE (Erase Location): Figure 3.8 EEPROM ERASE Cycle ERAL (Erase All): Figure 3.9 EEPROM ERAL Cycle EWDS (Erase/Write Disable): Figure 3.10 EEPROM EWDS Cycle EWEN (Erase/Write Enable): EECS EECLK READ (Read Location): Figure 3.12 EEPROM READ Cycle WRITE (Write Location): Figure 3.13 EEPROM WRITE Cycle WRAL (Write All): Figure 3.14 EEPROM WRAL Cycle Table 3.4 Required EECLK Cycles OPERATION REQUIRED EECLK CYCLES 3.4DMA Controller (DMAC) Page Ring Structure: Chain Structure: Figure 3.15 Ring and Chain Descriptor Structures 3.4.2.1Receive Descriptors Receive Descriptor 0 (RDES0) Table 3.5 RDES0 Bit Fields (continued) FL - Frame Length ES - Error Summary DE - Descriptor Error LE - Length Error TL - Frame Too Long CS - Collision Seen FT - Frame Type RW – Receive Watchdog ME - MII Error Receive Descriptor 1 (RDES1) Receive Descriptor 2 (RDES2) Receive Descriptor 3 (RDES3) 3.4.2.2Transmit descriptors Transmit Descriptor 0 (TDES0) Transmit Descriptor 1 (TDES1) Table 3.10 TDES1 Bit Fields (continued) CK - TX Checksum Enable AC - Add CRC Disable TER - Transmit End of Ring TCH - Second Address Chained Transmit Descriptor 2 (TDES2) Transmit Descriptor 3 (TDES3) 3.4.4Transmit Operation 3.4.5Receive Operation 3.4.6Receive Descriptor Acquisition 3.4.7.1Transmit Engine 3.4.7.2Receive Engine 3.4.9.1Calculating Worst-CaseTX FIFO (MIL) Usage 3.510/100 Ethernet MAC 3.5.1.1Full-DuplexFlow Control Figure 3.18 VLAN Frame 3.5.3Address Filtering Functional Description Table 3.13 Address Filtering Modes MCPAS PRMS INVFILT 3.5.3.1Perfect Filtering 3.5.3.2Hash Only Filtering Mode 3.5.3.3Hash Perfect Filtering 3.5.3.4Inverse Filtering 3.5.4Wakeup Frame Detection Table 3.14 Wakeup Frame Filter Register Structure Table 3.15 Filter i Byte Mask Bit Definitions FILTER i BYTE MASK DESCRIPTION BITS DESCRIPTION 31RESERVED Byte Mask: 3.5.4.1Magic Packet Detection 3.5.5Receive Checksum Offload Engine (RXCOE) Figure 3.19 RXCOE Checksum Calculation Page Figure 3.23 Ethernet Frame with VLAN Tag and SNAP Header Figure 3.24 Ethernet Frame with multiple VLAN Tags and SNAP Header 3.5.5.1RX Checksum Calculation 3.5.6.1TX Checksum Calculation 3.610/100 Ethernet PHY 3.6.1.14B/5B Encoding 3.6.1.2Scrambling 3.6.1.3NRZI and MLT3 Encoding 3.6.1.4100M Transmit Driver 3.6.1.5100M Phase Lock Loop (PLL) 3.6.2.1100M Receive Input 3.6.2.2Equalizer, Baseline Wander Correction and Clock and Data Recovery 3.6.2.3NRZI and MLT-3Decoding 3.6.2.4Descrambling 3.6.2.5Alignment 3.6.2.65B/4B Decoding 3.6.2.7Receiver Errors 3.6.3.110M Transmit Data Across the Internal MII Bus 3.6.3.2Manchester Encoding 3.6.3.310M Transmit Drivers 3.6.4.110M Receive Input and Squelch 3.6.4.2Manchester Decoding 3.6.4.3Jabber Detection 3.6.6.1Re-starting Auto-negotiation 3.6.6.2Disabling Auto-negotiation 3.6.6.3Half vs. Full-Duplex 3.6.8.1General Power-Down 3.6.8.2Energy Detect Power-Down 3.6.9.1PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST) 3.6.9.2PHY Soft Reset via PHY Basic Control Register bit 15 (PHY Reg. 0.15) 3.7Power Management 3.7.2Related External Signals and Power Supplies Note: 3.7.4.1G3 State (Mechanical Off) State (D0 3.7.4.3D0ACTIVE State (D0A) 3.7.4.4The D3HOT State 3.7.4.5The D3COLD State 3.7.5Resets Table 3.22 Reset Map BLOCK POR PCInRST 3.7.5.1PHY Resets 3.7.6.1Enabling Wakeup Frame Wake Events Page Chapter 4 Register Descriptions Page 4.1Register Nomenclature 4.2System Control and Status Registers (SCSR) 4.2.1ID and Revision (ID_REV) Chip ID Block Revision 4.2.2Interrupt Control Register (INT_CTL) Software Interrupt Enable (SW_INT_EN) Master Bus Error Interrupt Enable (MBERR_INT_EN) Slave Bus Error Interrupt Enable (SBERR_INT_EN) GPIO [2:0] (GPIOx_INT_EN) 4.2.3Interrupt Status Register (INT_STS) Software Interrupt (SW_INT) Master Bus Error Interrupt (MBERR_INT) Slave Bus Error Interrupt (SBERR_INT) GPIO [2:0] (GPIOx_INT) Wake Event Interrupt (WAKE_INT) DMAC Interrupt (DMAC_INT) 4.2.4Interrupt Configuration Register (INT_CFG) Master Interrupt (IRQ_INT) IRQ Enable (IRQ_EN) Interrupt De-assertionInterval Clear (INT_DEAS_CLR) Interrupt De-assertionStatus (INT_DEAS_STS) 4.2.5General Purpose Input/Output Configuration Register (GPIO_CFG) LED[3:1] enable (LEDx_EN) GPIO Interrupt Polarity 0-2(GPIO_INT_POL) EEPROM Enable (EEPR_EN) GPIO Buffer Type 0-2(GPIOBUFn) GPIO Direction 0-2(GPDIRn) GPO Data 3-4(GPODn) GPIO Data 0-2(GPIODn) Table 4.3 EEPROM Enable Bit Definitions [22] 4.2.6General Purpose Timer Configuration Register (GPT_CFG) General Purpose Timer Enable (TIMER_EN) General Purpose Timer Pre-Load(GPT_LOAD) 4.2.7General Purpose Timer Current Count Register (GPT_CNT) General Purpose Timer Current Count (GPT_CNT) 4.2.8Bus Master Bridge Configuration Register (BUS_CFG) RX/TX Arbitration Priority Select (CSR_RXTXWEIGHT) 4.2.9Power Management Control Register (PMT_CTRL) PHY Reset (PHY_RST) Wake-On-LanWakeup Enable (WOL_EN) Energy-DetectWakeup Enable (ED_EN) Wakeup Status (WUPS) Free Run Counter (FREE_RUN) Free Running Counter (FR_CNT) 4.2.11EEPROM Command Register (E2P_CMD) EPC Busy (EPC_BSY) EPC Command (EPC_CMD) [30:28] = 000; [30:28] = 001; [30:28] = 010; [30:28] = 011; EEPROM Loaded EPC Address (EPC_ADDR) 4.2.12EEPROM Data Register (E2P_DATA) EEPROM Data 4.3DMAC Control and Status Registers (DCSR) Bus Mode Register (BUS_MODE) Programmable Burst Length (PBL) Descriptor Skip Length (DSL) Bus Arbitration (BAR) Software Reset (SRST) 4.3.2Transmit Poll Demand Register (TX_POLL_DEMAND) Transmit Poll Demand (TPD) 4.3.3Receive Poll Demand Register (RX_POLL_DEMAND) Receive Poll Demand (RPD) 4.3.4Receive List Base Address Register (RX_BASE_ADDR) Start of Receive List (SRL) 4.3.5Transmit List Base Address Register (TX_BASE_ADDR) Start of Transmit List (STL) 4.3.6DMA Controller Status Register (DMAC_STATUS) Transmit Process State (TS) Receive Process State (RS) Normal Interrupt Summary (NIS) Abnormal Interrupt Summary (AIS) Receive Watchdog Timeout (RWT) Receive Process Stopped (RPS) Receive Buffer Unavailable (RU) Receive Interrupt (RI) Transmit Buffer Unavailable (TU) 4.3.7DMA Controller Control (Operation Mode) Register (DMAC_CONTROL) Must Be One (MBO) Start/Stop Transmission Command (ST) Operate on Second Frame (OSF) Start/Stop Receive (SR) 4.3.8DMA Controller Interrupt Enable Register (DMAC_INTR_ENA) Normal Interrupt Summary Enable (NIS_EN) Abnormal Interrupt Summary Enable (AIS_EN) Receive Watchdog Timeout (RWT_EN) Receive Process Stopped (RPS_EN) Transmit Process Stopped (TPS_EN) Transmit Interrupt (TI_EN) 4.3.9Missed Frame and Buffer Overflow Counter Reg (MISS_FRAME_CNTR) MIL RX FIFO Full Counter Overflow (MIL_OVER) MIL RX FIFO Full Counter (MIL_FIFO_FULL) RX Buffer Unavailable Counter Overflow (UNAV_OVER) RX Buffer Unavailable Counter (RX_BUFF_UNAV) 4.3.10Current Transmit Buffer Address Register (TX_BUFF_ADDR) TX_BUFF_ADDR 4.3.11Current Receive Buffer Address Register (RX_BUFF_ADDR) RX_BUFF_ADDR 4.4MAC Control and Status Registers (MCSR) 4.4.1MAC Control Register (MAC_CR) Receive All Mode (RXALL) Disable Receive Own (RCVOWN) Loopback operation Mode (LOOPBK) Full Duplex Mode (FDPX) Hash Only Filtering mode (HO) Hash/Perfect Filtering Mode (HPFILT) Late Collision Control (LCOLL) Disable Broadcast Frames (BCAST) Disable Retry (DISRTY) BackOff Limit (BOLMT) Deferral Check (DFCHK) Transmitter enable (TXEN) Receiver Enable (RXEN) 4.4.2MAC Address High Register (ADDRH) Physical Address [47:32] 4.4.3MAC Address Low Register (ADDRL) Physical Address [31:0] Table 4.6 ADDRL, ADDRH Byte Ordering ADDRL, ADDRH ORDER OF RECEPTION ON ETHERNET 4.4.4Multicast Hash Table High Register (HASHH) Upper 32 bits of the 64-bitHash Table 4.4.5Multicast Hash Table Low Register (HASHL) Lower 32 bits of the 64-bitHash Table 4.4.6MII Access Register (MII_ACCESS) PHY Address MII Register Index (MIIRINDA) MII Write (MIIWnR) MII Busy (MIIBZY) 4.4.7MII Data Register (MII_DATA) MII Data 4.4.8Flow Control Register (FLOW) Pause Time (FCPT) Pass Control Frames (FCPASS) Flow Control Enable (FCEN) Flow Control Busy (FCBSY) 4.4.9VLAN1 Tag Register (VLAN1) VLAN1 Tag Identifier (VTI1) 4.4.10VLAN2 Tag Register (VLAN2) VLAN2 Tag Identifier (VTI2) Wakeup Frame Filter (WUFF) Wakeup Frame Filter (WFF) 4.4.12Wakeup Control and Status Register (WUCSR) Global Unicast Enable (GUE) Remote Wakeup Frame Received (WUFR) Magic Packet Received (MPR) Wakeup Frame Enable (WAKE_EN) 4.4.13Checksum Offload Engine Control Register (COE_CR) TX Checksum Offload Engine Enable (TX_COE_EN) RX Checksum Offload Engine Mode (RX_COE_MODE) RX Checksum Offload Engine Enable (RX_COE_EN) 4.5PHY Registers Basic Control Register PHY Soft Reset Loopback Speed Select Auto-NegotiationEnable Basic Status Register 100BASE-T4 100BASE-TXFull Duplex 100BASE-TXHalf Duplex 10BASE-TFull Duplex PHY ID Number PHY ID Number b Model Number Revision Number Auto Negotiation Advertisement Pause Operation (See Note 4.5) 100BASE-TX 10BASE-T Selector Field Auto Negotiation Link Partner Ability Next Page Acknowledge Pause Operation Auto Negotiation Expansion Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Mode Control/Status EDPWRDOWN ENERGYON Special Modes PHYADD Table 4.8 MODE Control DEFAULT REGISTER BIT VALUES MODE DEFINITIONS 4.5.10Special Control/Status Indications Override AUTOMDIX_EN Strap Auto-MDIXEnable Auto-MDIXState VCOOFF_LP Interrupt Source Flag INT7 INT6 INT5 INT4 Interrupt Mask Mask Bits PHY Special Control/Status Autodone Speed Indication 4.6PCI Configuration Space CSR (CONFIG CSR) YES Table 4.10 Standard PCI Header Registers Supported READ EEPROM SPACE OFFSET 4.6.1PCI Power Management Capabilities Register (PCI_PMC) PME Support from D3COLD (PME_IN_D3C) PME Support from D3HOT (PME_IN_D3H) PME Support from D2 (PME_IN_D2) PME Support from D1 (PME_IN_D1) Power Management Specification Version (VERSION[2:0]) Next Item Offset (NEXT_OFFSET[7:0]) Capability ID (CAP_ID) 4.6.2PCI Power Management Control and Status Register (PCI_PMCSR) Data (PM_DATA) PMCSR PCI to PCI Bridge Support Extensions (PMCSR_BSE) PME Status (PME_STATUS) Data Scale (DATA_SCALE) Power Management State (PM_STATE) 00b = D0 01b = RESERVED Chapter 5 Operational Characteristics 5.1Absolute Maximum Ratings 5.2Operating Conditions 5.3Power Consumption 5.3.2D3 - Enabled for Wake Up Packet Detection 5.3.3D3 - Enabled for Link Status Change Detection (Energy Detect) 5.3.4D3 - PHY in General Power Down Mode Table 5.4 D3 - PHY in General Power Down Mode - Supply and Current (Typical) 5.3.5Maximum Power Consumption Table 5.5 Maximum Power Consumption - Supply and Current (Maximum) MAXIMUM 5.4DC Specifications Table 5.7 100BASE-TXTransceiver Characteristics Table 5.8 10BASE-TTransceiver Characteristics 5.5AC Specifications 5.6PCI Clock Timing 5.7PCI I/O Timing Table 5.11 PCI I/O Timing Values 5.8EEPROM Timing 5.9Clock Circuit Chapter 6 Package Outline 6.1128-VTQFPPackage Table 6.1 LAN9420/LAN9420i 128-VTQFPDimensions NOMINAL REMARKS Notes: Figure 6.2 LAN9420/LAN9420i 128-VTQFPRecommended PCB Land Pattern Chapter 7 Revision History