SMSC LAN9420, LAN9420i 3.2.3.1PCI Master Transaction Errors, 3.2.3PCI Master Interface, 3.2.2PCI Interface Environments, Note:, Figure 3.2 Device Operation

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

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3.2.2PCI Interface Environments

The PCIB supports only Device operation. It functions as a simple bridge, permitting LAN9420/LAN9420i to act as a master/target PCI device on the PCI bus. The Host performs PCI arbitration and is responsible for initializing configuration space for all devices on the bus. Figure 3.2 illustrates Device operation.

			Host
			System
	PCI
	Bus
				PCIB
PCI		PCI		LAN9420	PCI
Component		Component			Component

Figure 3.2 Device Operation

3.2.3PCI Master Interface

The PCI Master Interface is used by the DMA engines to directly access the PCI Host’s memory. It is used by the TX and RX DMA Controllers to access Host descriptor ring elements and Host DMA buffers. No address translation occurs, as these entities are contained within the Host, which allocates them within the flat PCI address space.

3.2.3.1PCI Master Transaction Errors

In the event of an error during a descriptor read or during a transmit data read, the DMA controller will generate a Master Bus Error Interrupt (MBERR_INT).

When an MBERR_INT is asserted, all subsequent transactions from the DMAC will be aborted. In order to cleanly recover from this condition, a software reset or H/W reset must be performed. A software reset is accomplished by setting the SRST bit of the BUS_MODE register.

Note: It is guaranteed that the MBERR_INT will be reported on the frame upon which the error occurred as follows:

-Errors on descriptor reads will be aborted immediately.

-Errors on TX data will be reported either upon the data or the close descriptor (if the error occurs on the last data transfer).

-DMA RX data and descriptor write operations are posted and will therefore not generate the MBERR_INT.

SMSC LAN9420/LAN9420i	25	Revision 1.22 (09-25-08)
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