Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

BITS

 

 

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

 

 

 

 

7-6

BackOff Limit (BOLMT)

 

 

 

R/W

00b

 

The BOLMT bits allow the user to set its back-off limit in a relaxed or

 

 

 

aggressive mode. According to IEEE 802.3, the MAC has to wait for a

 

 

 

random number [r] of slot-times (Note 4.4) after it detects a collision, where:

 

 

 

(eq.1)0 < r < 2K

 

 

 

 

 

 

The exponent K is dependent on how many times the current frame to be

 

 

 

transmitted has been retried, as follows:

 

 

 

(eq.2)K = min (n, 10) where n is the current number of retries.

 

 

 

If a frame has been retried three times, then K = 3 and r= 8 slot-times

 

 

 

maximum. If it has been retried 12 times, then K = 10, and r = 1024 slot-

 

 

 

times maximum.

 

 

 

 

 

 

An LFSR (linear feedback shift register) 20-bit counter emulates a 20bit

 

 

 

random number generator, from which r is obtained. Once a collision is

 

 

 

detected, the number of the current retry of the current frame is used to

 

 

 

obtain K (eq.2). This value of K translates into the number of bits to use

 

 

 

from the LFSR counter. If the value of K is 3, the MAC takes the value in

 

 

 

the first three bits of the LFSR counter and uses it to count down to zero

 

 

 

on every slot-time. This effectively causes the MAC to wait eight slot-times.

 

 

 

To give the user more flexibility, the BOLMT value forces the number of bits

 

 

 

to be used from the LFSR counter to a predetermined value as in the table

 

 

 

below.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BOLMT Value

 

# Bits Used from LFSR Counter

 

 

 

 

 

 

 

 

 

 

 

 

 

2’b00

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

2’b01

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

2’b10

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

2’b11

 

1

 

 

 

 

 

 

 

 

 

 

 

Thus, if the value of K = 10, the MAC will look at the BOLMT if it is 00, then use

 

 

 

the lower ten bits of the LFSR counter for the wait countdown. If the BOLMT is 10,

 

 

 

then it will only use the value in the first four bits for the wait countdown, etc.

 

 

 

Note 4.4 Slot-time = 512 bit times. (See IEEE 802.3 Spec., Secs. 4.2.3.25

 

 

 

 

and 4.4.2.1)

 

 

 

 

 

 

 

 

 

 

 

 

 

5

Deferral Check (DFCHK)

 

 

 

R/W

0b

 

When set, enables the deferral check in the MAC. The MAC will abort the

 

 

 

transmission attempt if it has deferred for more than 24,288 bit times.

 

 

 

Deferral starts when the transmitter is ready to transmit, but is prevented

 

 

 

from doing so because the CRS is active. Defer time is not cumulative. If

 

 

 

the transmitter defers for 10,000 bit times, then transmits, collides, backs

 

 

 

off, and then has to defer again after completion of back-off, the deferral

 

 

 

timer resets to 0 and restarts. When reset, the deferral check is disabled in

 

 

 

the MAC and the MAC defers indefinitely.

 

 

 

 

 

 

 

 

 

 

4

RESERVED

 

 

 

RO

-

 

 

 

 

 

 

 

 

3

Transmitter enable (TXEN)

 

 

 

R/W

0b

 

When set, the MAC’s transmitter is enabled and it will transmit frames from

 

 

 

the buffer onto the cable. When reset, the MAC’s transmitter is disabled and

 

 

 

will not transmit any frames.

 

 

 

 

 

 

 

 

 

 

 

 

 

SMSC LAN9420/LAN9420i

121

Revision 1.22 (09-25-08)

 

DATASHEET