SMSC LAN9420, LAN9420i 4.4.4Multicast Hash Table High Register (HASHH), BITS, TYPE, DEFAULT, DESCRIPTION, Upper 32 bits of the 64-bitHash Table

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

4.4.4Multicast Hash Table High Register (HASHH)

Offset: 008Ch Size: 32 bits

The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the Hash table. The most significant bit determines the register to be used (Hi/Low), while the other five bits determine the bit within the register. A value of 00000 selects Bit 0 of the Multicast Hash Table Lo register and a value of 11111 selects the Bit 31 of the Multicast Hash Table Hi register.

If the corresponding bit is 1, then the multicast frame is accepted. Otherwise, it is rejected. If the “Pass All Multicast” (MCPAS) bit is set (1), then all multicast frames are accepted regardless of the multicast hash values.

The Multicast Hash Table Hi register contains the higher 32 bits of the hash table and the Multicast Hash Table Low register contains the lower 32 bits of the hash table.

BITS	DESCRIPTION	TYPE	DEFAULT
31-0	Upper 32 bits of the 64-bit Hash Table	R/W	32‘h0

SMSC LAN9420/LAN9420i	125	Revision 1.22 (09-25-08)
	DATASHEET