Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

4.2.4Interrupt Configuration Register (INT_CFG)

Offset:

00CCh

Size:

32 bits

This register configures and monitors the interrupt (IRQ) signal.

Control of the de-assertion interval for the IRQ is also included. The de-assertion interval is the minimum time the IRQ will remain de-asserted after it has been asserted and cleared. After this time period has elapsed, the IRQ will be asserted if the interrupt is active. This interval begins counting when interrupt sources have been cleared from the asserted state. Refer to Section 3.3.1, "Interrupt Controller," on page 28 for more information on the Interrupt Controller.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:20

RESERVED

RO

-

 

 

 

 

19

Master Interrupt (IRQ_INT)

RO

0b

 

This read-only bit indicates the state of the IRQ line. When set high, one of

 

 

 

the enabled interrupts is currently active. This bit will respond to the

 

 

 

associated interrupts regardless of the IRQ_EN field. This bit is not affected

 

 

 

by the setting of the INT_DEAS field.

 

 

 

 

 

 

18

IRQ Enable (IRQ_EN)

R/W

0b

 

When cleared, the IRQ output to the PCIB is disabled and will be

 

 

 

permanently de-asserted. When set, the IRQ output functions normally.

 

 

 

 

 

 

17:10

RESERVED

RO

-

 

 

 

 

9

Interrupt De-assertion Interval Clear (INT_DEAS_CLR)

R/W/SC

0b

 

Writing a one to this register clears the de-assertion counter in the Interrupt

 

 

 

Controller, thus causing a new de-assertion interval to begin (regardless of

 

 

 

whether or not the Interrupt Controller is currently in an active de-assertion

 

 

 

interval).

 

 

 

 

 

 

8

Interrupt De-assertion Status (INT_DEAS_STS)

RO

0b

 

When set, this bit indicates that the INT_DEAS is currently in a de-assertion

 

 

 

interval, and any interrupts (as indicated by the IRQ_INT and INT_EN bits)

 

 

 

will not be delivered to the IRQ. When cleared, the INT_DEAS is currently

 

 

 

not in a de-assertion interval, and enabled interrupts will be delivered to the

 

 

 

IRQ.

 

 

 

 

 

 

7:0

Interrupt De-assertion Interval (INT_DEAS)

R/W

00h

 

This field determines the interrupt de-assertion interval for the IRQ in

 

 

 

multiples of 10 microseconds.

 

 

 

Writing zeros to this field disables the INT_DEAS interval and resets the

 

 

 

interval counter. Any pending interrupts are then issued. If a new, non-zero

 

 

 

value is written to the INT_DEAS field, any subsequent interrupts will obey

 

 

 

the new setting.

 

 

 

Note: The interrupt de-assertion interval does not apply to the wake

 

 

 

interrupt.

 

 

 

 

 

 

SMSC LAN9420/LAN9420i

91

Revision 1.22 (09-25-08)

 

DATASHEET