Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

 

 

 

 

 

 

Datasheet

4.4.11

Wakeup Frame Filter (WUFF)

 

 

 

 

 

Offset:

00A8h

Size:

32 bits

 

 

This register is used to configure the Wakeup Frame Filter.

 

 

 

 

 

 

 

 

 

 

BITS

 

DESCRIPTION

 

 

TYPE

DEFAULT

 

 

 

 

 

 

 

31:0

Wakeup Frame Filter (WFF)

 

 

 

R/W

0000_0000h

 

The Wakeup Frame Filter is configured through this register using an

 

 

 

indexing mechanism. Following a reset, the MAC loads the first value

 

 

 

written to this location to the first DWORD in the Wakeup Frame Filter (filter

 

 

 

0 byte mask). The second value written to this location is loaded to the

 

 

 

second DWORD in the wakeup Frame Filter (filter 1 byte mask) and so on.

 

 

 

Once all eight DWORDs have been written, the internal pointer will once

 

 

 

again point to the first entry and the filter entries can be modified in the

 

 

 

same manner. Similarly, eight DWORDS should be read sequentially to

 

 

 

obtain the values stored in the WFF.

 

 

 

 

 

Note: This register should be read and written using eight consecutive

 

 

 

DWORD operations. Failure to read or write the entire contents of

 

 

 

the WFF may cause the internal read/write pointers to be left in a

 

 

 

position other than pointing to the first entry.

 

 

 

 

 

 

 

 

 

 

Revision 1.22 (09-25-08)

132

SMSC LAN9420/LAN9420i

 

DATASHEET