Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

4.2.6General Purpose Timer Configuration Register (GPT_CFG)

Offset:

00D4h

Size:

32 bits

This register configures the general purpose timer (GPT). The GPT can be configured to generate interrupts at intervals defined in this register. Refer to Section 3.3.3, "General Purpose Timer (GPT)," on page 30 for more information on the General Purpose Timer.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:30

RESERVED

RO

-

 

 

 

 

29

General Purpose Timer Enable (TIMER_EN)

R/W

0b

 

When a one is written to this bit the GPT is put into the run state. When

 

 

 

cleared, the GPT is halted. On the 1-to-0 transition of this bit the

 

 

 

GPT_LOAD field will be preset to FFFFh.

 

 

 

 

 

 

28:16

RESERVED

RO

-

 

 

 

 

15:0

General Purpose Timer Pre-Load (GPT_LOAD)

R/W

FFFFh

 

This value is pre-loaded into the GPT. See Section 3.3.3, "General Purpose

 

 

 

Timer (GPT)," on page 30 for more details.

 

 

 

 

 

 

Revision 1.22 (09-25-08)

94

SMSC LAN9420/LAN9420i

 

DATASHEET