SMSC LAN9420, LAN9420i 5.7PCI I/O Timing, VALUE, UNITS, Note:, SYMBOL, Figure 5.3 PCI I/O Timing, Table 5.10 PCI I/O Timing Measurement Conditions

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

5.7PCI I/O Timing

The following specifies the PCI I/O requirements for LAN9420/LAN9420i:

PCICLK			Vth
			Vtest
			Vtl
	tval
PCI OUTPUTS		Vtrise, Vtfall
	ton		toff
TRI-STATE PCI
OUTPUTS
		tsu	th
PCI INPUTS	Vmax	Vtest	Vth
			Vtl
	Figure 5.3 PCI I/O Timing
Table 5.10 PCI I/O Timing Measurement Conditions
SYMBOL		VALUE	UNITS
Vth		0.6*VDD33IO	V
Vtl		0.2*VDD33IO	V
Vtest		0.4*VDD33IO	V
Vtrise		0.285*VDD33IO	V
Vtfall		0.615*VDD33IO	V
Vmax		0.4*VDD33IO	V
Input Signal Edge Rate		1	V/ns

Note: Input test is done with 0.1*VDD33IO overdrive. Vmax specifies the maximum peak-to-peak waveform allowed for testing input timing.

SMSC LAN9420/LAN9420i	163	Revision 1.22 (09-25-08)
	DATASHEET