Datasheet
2.1Pin List
Table 2.1 PCI Bus Interface PinsNUM |
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| BUFFER |
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PINS | NAME | SYMBOL | TYPE |
| DESCRIPTION |
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1 | PCI Clock In | PCICLK | IS | PCI Clock In: 0 to 33MHz PCI Clock Input. | |
1 | PCI Frame | nFRAME | IPCI/ | PCI Cycle Frame | |
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| OPCI |
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32 | PCI Address | AD[31:0] | IPCI/ | PCI Address and Data Bus | |
| and Data Bus |
| OPCI |
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1 | PCI Reset | PCInRST | IS | PCI Reset | |
4 | PCI Bus | nCBE[3:0] | IPCI/ | PCI Bus Command and Byte Enables | |
| Command and |
| OPCI |
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| Byte Enables |
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1 | PCI Initiator | nIRDY | IPCI/ | PCI Initiator Ready | |
| Ready |
| OPCI |
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1 | PCI Target | nTRDY | IPCI/ | PCI Target Ready | |
| Ready |
| OPCI |
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1 | PCI Stop | nSTOP | IPCI/ | PCI Stop | |
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| OPCI |
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1 | PCI Device | nDEVSEL | IPCI/ | PCI Device Select | |
| Select |
| OPCI |
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1 | PCI Parity | PAR | IPCI/ | PCI Parity | |
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| OPCI |
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1 | PCI Parity | nPERR | IPCI/ | PCI Parity Error | |
| Error |
| OPCI |
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1 | PCI System | nSERR | IPCI/ | PCI System Error | |
| Error |
| OPCI |
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1 | PCI Interrupt | nINT | OPCI | PCI Interrupt | |
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| Note: | This pin is an open drain output. |
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| |
1 | PCI IDSEL | IDSEL | IPCI | PCI IDSEL | |
1 | PCI Request | nREQ | OPCI | PCI Request | |
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| Note: | This pin is a |
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1 | PCI Grant | nGNT | IPCI | PCI Grant | |
1 | PCI Power | nPME | OPCI | PCI Power Management Event | |
| Management |
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| Note: | This pin is an open drain output. |
| Event |
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1 | Power Good | PWRGOOD | IS | PCI Bus Power Good: This pin is used to sense the | |
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| (PD) | presence of PCI bus power during the D3 power | |
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| management state. | |
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| Note: | This pin is pulled low through an internal pull- |
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| down resistor |
1 | VAUX Detection | VAUXDET | IS | PCI Auxiliary Voltage Sense: This pin is used to sense | |
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| (PD) | the presence of a 3.3V auxiliary supply in order to define | |
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| the PME support available. | |
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| Note: | This pin is pulled low through an internal pull- |
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| down resistor |
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Revision 1.22 | 16 | SMSC LAN9420/LAN9420i |
| DATASHEET |
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