Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

2.1Pin List

Table 2.1 PCI Bus Interface Pins
NUM

 

 

BUFFER

 

 

PINSNAMESYMBOL

TYPE

 

DESCRIPTION

 

 

 

 

 

1

PCI Clock In

PCICLK

IS

PCI Clock In: 0 to 33MHz PCI Clock Input.

1

PCI Frame

nFRAME

IPCI/

PCI Cycle Frame

 

 

 

OPCI

 

 

32

PCI Address

AD[31:0]

IPCI/

PCI Address and Data Bus

 

and Data Bus

 

OPCI

 

 

1

PCI Reset

PCInRST

IS

PCI Reset

4

PCI Bus

nCBE[3:0]

IPCI/

PCI Bus Command and Byte Enables

 

Command and

 

OPCI

 

 

 

Byte Enables

 

 

 

 

1

PCI Initiator

nIRDY

IPCI/

PCI Initiator Ready

 

Ready

 

OPCI

 

 

1

PCI Target

nTRDY

IPCI/

PCI Target Ready

 

Ready

 

OPCI

 

 

1

PCI Stop

nSTOP

IPCI/

PCI Stop

 

 

 

OPCI

 

 

1

PCI Device

nDEVSEL

IPCI/

PCI Device Select

 

Select

 

OPCI

 

 

1

PCI Parity

PAR

IPCI/

PCI Parity

 

 

 

OPCI

 

 

1

PCI Parity

nPERR

IPCI/

PCI Parity Error

 

Error

 

OPCI

 

 

1

PCI System

nSERR

IPCI/

PCI System Error

 

Error

 

OPCI

 

 

1

PCI Interrupt

nINT

OPCI

PCI Interrupt

 

 

 

 

Note:

This pin is an open drain output.

 

 

 

 

 

1

PCI IDSEL

IDSEL

IPCI

PCI IDSEL

1

PCI Request

nREQ

OPCI

PCI Request

 

 

 

 

Note:

This pin is a tri-state output.

 

 

 

 

 

1

PCI Grant

nGNT

IPCI

PCI Grant

1

PCI Power

nPME

OPCI

PCI Power Management Event

 

Management

 

 

Note:

This pin is an open drain output.

 

Event

 

 

 

 

 

 

 

1

Power Good

PWRGOOD

IS

PCI Bus Power Good: This pin is used to sense the

 

 

 

(PD)

presence of PCI bus power during the D3 power

 

 

 

 

management state.

 

 

 

 

Note:

This pin is pulled low through an internal pull-

 

 

 

 

 

down resistor

1

VAUX Detection

VAUXDET

IS

PCI Auxiliary Voltage Sense: This pin is used to sense

 

 

 

(PD)

the presence of a 3.3V auxiliary supply in order to define

 

 

 

 

the PME support available.

 

 

 

 

Note:

This pin is pulled low through an internal pull-

 

 

 

 

 

down resistor

 

 

 

 

 

 

Revision 1.22 (09-25-08)

16

SMSC LAN9420/LAN9420i

 

DATASHEET