SMSC LAN9420, LAN9420i Figure 3.6 Interrupt Controller Block Diagram

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

„General-purpose timer interrupt (GPT_INT)

„General purpose Input/Output interrupt (GPIOx_INT)

„Software interrupt (SW_INT)

„Master bus error interrupt (MBERR_INT)

„Slave bus error interrupt (SBERR_INT)

„Wake event detection (WAKE_INT)

A Block diagram of the Interrupt Controller is shown in Figure 3.6

.

Interrupt Controller

		SW_INT
SW_INT_EN		(INT_STS Register)
	RW	0 to 1
(INT_CTL Register)		DETECT
	MBERR_INT
Master Bus Error	(INT_STS Register)
Interrupt
MBERR_INT_EN	RW
(INT_CTL Register)
	SBERR_INT
Slave Bus Error	(INT_STS Register)
Interrupt
SBERR_INT_EN	RW
(INT_CTL Register)
	GPIO2_INT
	(INT_STS Register)
GPIO2 Interrupt
GPIO2_INT_EN	RW
(INT_CTL Register)
	GPIO1_INT
	(INT_STS Register)
GPIO1 Interrupt
GPIO1_INT_EN	RW
(INT_CTL Register)
	GPIO0_INT
	(INT_STS Register)
GPIO0 Interrupt
GPIO0_INT_EN	RW
(INT_CTL Register)
	GPT_INT
	(INT_STS Register)
GP Timer Interrupt
GPT_INT_EN	RW
(INT_CTL Register)
	RO	PHY_INT
		(INT_STS Register)
PHY Interrupt
PHY_INT_EN	RW
(INT_CTL Register)
	RO	DMAC_INT
		(INT_STS Register)
DMAC Interrupt

WAKE_INT

RO (INT_STS Register)

Wake Event Interrupt

WAKE_INT_EN (INT_CTL Register) RW

INT_DEAS[7:0]	RW	RO	INT_DEAS_STS
(INT_CFG Register)			(INT_CFG Register)
INT_DEAS_CLR	RW	DEASSERTION
(INT_CFG Register)		TIMER

IRQ_EN (INT_CTL Register) RW

IRQ_INT

(INT_CFG Register)

RO

IRQ

(PCIB)

Figure 3.6 Interrupt Controller Block Diagram

The Interrupt Controller control and status register are contained within the System Control and Status Registers (SCSR) block. The interrupt status register (INT_STS) reflects the current state of the interrupt sources prior to qualification with their associated enables. The SW_INT, MBERR_INT, SBERR_INT, GPIOx_INT, and GPT_INT are latched, and are cleared through the SCSR block upon a

SMSC LAN9420/LAN9420i	29	Revision 1.22 (09-25-08)
	DATASHEET