Datasheet
4.3.6DMA Controller Status Register (DMAC_STATUS)Offset: | 0014h | Size: | 32 bits |
This register contains all of the status bits that the DMAC reports to the Host system. Most of the fields in this register will cause an interrupt. Status can be checked as part of an interrupt service routine, or by polling. DMAC interrupts can be masked in the DMAC_INTR_ENA register.
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31:23 | RESERVED |
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22:20 | Transmit Process State (TS) | RO | 000b | |||||
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| STATE | DESCRIPTION |
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| 000 | Stopped - Reset or Stop command issued |
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| 001 | Running - Fetching the transmit descriptor |
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| 010 | Running - Waiting for the end of transmission |
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| 011 | Running - Reading the data from memory and queuing into TX FIFO |
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| 100 | RESERVED |
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| 101 | RESERVED |
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| 110 | Suspended - Unavailable transmit descriptor |
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| 111 | Running - Closing the transmit descriptor |
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19:17 | Receive Process State (RS) | RO | 000b | |||||
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| does not generate an interrupt. The RS field is encoded as follows: |
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| 000 | Stopped - Reset or Stop receive command |
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| 001 | Running - Fetching the receive descriptor |
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| 010 | Running - Checking for end of receive packet before prefetch of next |
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| 011 | Running - Waiting for receive packet |
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| 100 | Suspended - Unavailable receive descriptor |
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| 101 | Running - Closing receive descriptor |
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| 110 | Running - Flushing the current frame from the receive buffer because |
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| of unavailable receive buffer |
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| 111 | Running - Queuing the receive frame from the receive buffer into the |
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16 | Normal Interrupt Summary (NIS) | R/WC | 0b | |||||
| This bit is the logical OR of other bits within this register. Only unmasked |
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| bits affect this register. Below is the list of bits: |
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| DMAC_STATUS[0]: Transmit interrupt (TI) |
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| DMAC_STATUS[2]: Transmit buffer unavailable (TU) |
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| DMAC_STATUS[6]: Receive interrupt (RI) |
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15 | Abnormal Interrupt Summary (AIS) | R/WC | 0b | |||||
| This bit is the logical OR of other bits within this register. Only unmasked |
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| bits affect this register. Below is the list of bits: |
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| DMAC_STATUS[1]: Transmit process stopped (TPS) |
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| DMAC_STATUS[7]: Receive buffer unavailable (RU) |
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| DMAC_STATUS[8]: Receive process stopped (RPS) |
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SMSC LAN9420/LAN9420i | 109 | Revision 1.22 |
| DATASHEET |
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