Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

 

Datasheet

 

Transmit Descriptor 0 (TDES0)

 

TDES0 contains the transmitted frame status and the descriptor ownership information.

 

Table 3.9 TDES0 Bit Fields

 

 

BITS

DESCRIPTION

 

 

31

OWN - Own Bit

 

When set, indicates that the descriptor block and associated buffer(s) are owned by the DMA

 

controller. When reset, indicates that the descriptor block and associated buffer(s) are owned by

 

the Host system.

 

Host Actions: Checks this bit to determine ownership of the descriptor block and associated

 

buffer(s). The Host sets this bit to pass ownership to the DMAC. The Host does not modify a

 

descriptor block or access its associated buffer(s) until this bit is cleared by DMAC or until the

 

DMAC is in STOPPED state, whichever comes first. The ownership bit of the first descriptor of the

 

frame should be set after all subsequent descriptors belonging to the same frame have been set.

 

This avoids a possible race condition between the DMA controller fetching a descriptor and the Host

 

setting an ownership bit.

 

DMAC Actions: Reads this bit to determine ownership of the descriptor block and its associated

 

buffer(s). The DMAC clears this bit either when it completes the frame transmission or when the

 

buffers that are associated with this descriptor are empty. By clearing this bit, the DMAC closes the

 

descriptor block and passes ownership to the Host. If the DMAC fetches a descriptor with the OWN

 

bit cleared, the DMAC state machine enters the SUSPENDED state.

 

 

30:16

RESERVED

 

Host Actions: Cleared on writes and ignored on reads.

 

DMAC Actions: Ignored on reads and cleared on writes.

 

 

15

ES - Error Summary

 

Indicates the logical OR of the following TDES0 bits:

 

TDES0[2] – Excessive Deferral

 

TDES0[8] – Excessive collisions

 

TDES0[9] – Late collision

 

TDES0[10] – No carrier

 

TDES0[11] – Loss of carrier

 

Host Actions: Checks this bit to determine status.

 

DMAC Actions: Sets/clears this bit to define status.

 

 

14:12

RESERVED

 

Host Actions: Cleared on writes and ignored on reads.

 

DMAC Actions: Ignored on reads and cleared on writes.

 

 

11

LC - Loss of Carrier

 

When set, indicates loss of carrier during transmission.

 

Host Actions: Checks this bit to determine status.

 

DMAC Actions: Sets/clears this bit to define status.

 

 

10

NC - No Carrier

 

When set, indicates that the carrier signal from the transceiver was not present during transmission.

 

Host Actions: Checks this bit to determine status.

 

DMAC Actions: Sets/clears this bit to define status.

 

 

9

LT - Late Collision

 

When set, indicates that the frame transmission was aborted due to collision occurring after the

 

collision window of 64 bytes.

 

Host Actions: Checks this bit to determine status.

 

DMAC Actions: Sets/clears this bit to define status.

 

 

Revision 1.22 (09-25-08)

46

SMSC LAN9420/LAN9420i

 

DATASHEET