Datasheet
4.4.13Checksum Offload Engine Control Register (COE_CR)
| Offset: | 00B0h | Size: | 32 bits |
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| This register controls the RX and TX checksum offload engines. |
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| TYPE | DEFAULT |
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31:17 | RESERVED |
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| RO | - |
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16 | TX Checksum Offload Engine Enable (TX_COE_EN) |
| R/W | 0b | ||
| The COE_EN may only be changed if the TX path is disabled. If it is desired |
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| to disable the TX_COE_EN during run time, it is safe to do so only after the |
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| MAC is disabled and the MIL is empty. |
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| 0: The TXCOE is bypassed |
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| 1: The TXCOE is enabled |
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15:2 | RESERVED |
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| RO | - |
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1 | RX Checksum Offload Engine Mode (RX_COE_MODE) |
| R/W | 0b | ||
| This register indicates whether the COE will check for VLAN tags or a |
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| SNAP header prior to beginning its checksum calculation. In its default |
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| mode, the calculation will always begin 14 bytes into the frame. |
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| The COE_MODE may only be changed if the RX path is disabled. If it is |
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| desired to change this value during run time, it is safe to do so only after |
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| the MAC is disabled and the MIL is empty. |
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| 0: Begin checksum calculation after first 14 bytes of Ethernet Frame |
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| 1: Begin checksum calculation at start of L3 packet by adjusting for VLAN |
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| tags and/or SNAP header. |
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0 | RX Checksum Offload Engine Enable (RX_COE_EN) |
| R/W | 0b | ||
| The COE_EN may only be changed if the RX path is disabled. If it is |
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| desired to disable the COE_EN during run time, it is safe to do so only after |
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| the MAC is disabled and the MIL is empty. |
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| 0: The RXCOE is bypassed |
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| 1: The RXCOE is enabled |
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| Note: When the RXCOE is enabled, automatic pad stripping must be |
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| disabled (PADSTR bit of the MAC Control Register (MAC_CR)) |
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| and vice versa. These functions cannot be enabled |
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| simultaneously. |
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Revision 1.22 | 134 | SMSC LAN9420/LAN9420i |
| DATASHEET |
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