Datasheet
Bit 3 of the PCI Device Status Register. The PCI Device Status Register and PCI Device Command Register are standard registers in PCI Configuration Space. Please refer to Section 4.6, "PCI Configuration Space CSR (CONFIG CSR)," on page 149 for details.
Interrupt
Controller
PCIB
Bit 3
PCI Device
Status Register
IRQ | nINT | |
RW | ||
(To Host) | ||
|
Bit 10
PCI Device
Command Register
3.3System Control Block (SCB)
The System Control Block includes an interrupt controller, wake detection logic, a
Interrupt Controller: The interrupt controller can be programmed to interrupt the Host system applications on the occurrence of various events. The interrupt is routed to the Host system via the PCIB.
Wake Detection Logic: This logic detects the occurrence of an enabled wake event and asserts the PCI nPME signal, if enabled.
General Purpose Timer (GPT): The general purpose timer can be configured to generate a system interrupt upon timeout.
EEPROM Controller (EPC): An optional, external, Serial EEPROM may be used to store the default values for the MAC address, PCI Subsystem ID, and PCI Subsystem Vendor ID. In addition, it may also be used for general data storage. The EEPROM controller provides LAN9420/LAN9420i access to the EEPROM and permits the Host to read, write and erase its contents.
System Control and Status Registers (SCSR): These registers control system functions that are not specific to the DMAC, MAC or PHY.
3.3.1Interrupt Controller
The Interrupt Controller handles the routing of all internal interrupt sources. Interrupts enter the controller from various modules within LAN9420/LAN9420i. The Interrupt Controller drives the interrupt request (IRQ) output to the PCI Bridge. The Interrupt Controller is capable of generating PCI interrupts on detection of the following internal events:
DMAC interrupt request (DMAC_INT)
PHY interrupt request (PHY_INT)
Revision 1.22 | 28 | SMSC LAN9420/LAN9420i |
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