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Datasheet
3.7.3Device ClockingLAN9420/LAN9420i requires a
Internally, LAN9420/LAN9420i generates its required clocks with a
Please refer to Section 5.9, "Clock Circuit," on page 166 for more information on clock requirements.
3.7.4Power StatesThis section describes the operation of LAN9420/LAN9420i in each device power state (‘D’ states) as well as the events required to cause state transitions. LAN9420/LAN9420i’s behavior is dependant on the device’s VAUXDET pin (the device’s ability to detect wake events in D3COLD). Specific behaviors are discussed in the sections that follow.
Device power states and associated state transitions are illustrated in Figure 3.28 below. Note that Figure 3.28 includes the system’s mechanical off (G3) power state for illustrative purposes. This is the G3 state as defined by the ACPI specification. In this state all power (+3.3V and 3.3Vaux) is off.
T7
D0A
T2
T11
T3
T1 |
| 8 |
| T5, | T |
|
|
D0U
T9 T10
D3HOT | T4 | D3COLD | T6 | G3 | T12 Vaux Off |
Figure 3.28 LAN9420/LAN9420i Device Power States
Some power state transitions may place the PHY in the General
3.7.4.1G3 State (Mechanical Off)
G3 is not a device power state, but is discussed here for illustrative purposes. In the G3 state all PCI power is off. In this state all device context is lost.
3.7.4.1.1POWER MANAGEMENT EVENTS IN G3
LAN9420/LAN9420i does not detect power management events in the G3 state.
SMSC LAN9420/LAN9420i | 75 | Revision 1.22 |
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