Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

4.2.2Interrupt Control Register (INT_CTL)

Offset:

00C4h

Size:

32 bits

Interrupts are enabled/disabled through this register. Refer to Section 3.3.1, "Interrupt Controller," on page 28 for more information on the Interrupt Controller.

Note: The DMAC interrupt (DMAC_INT) is enabled through the DCSR.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:16

RESERVED

RO

-

 

 

 

 

15

Software Interrupt Enable (SW_INT_EN)

R/W

0b

 

On a transition from low to high, this register bit triggers the software

 

 

 

interrupt.

 

 

 

 

 

 

14

RESERVED

RO

-

 

 

 

 

13

Master Bus Error Interrupt Enable (MBERR_INT_EN)

R/W

0b

 

When set high, the Master Bus Error is enabled to generate an interrupt.

 

 

 

 

 

 

12

Slave Bus Error Interrupt Enable (SBERR_INT_EN)

R/W

0b

 

When set high, the Slave Bus Error is enabled to generate an interrupt.

 

 

 

 

 

 

11:7

RESERVED

RO

-

 

 

 

 

6:4

GPIO [2:0] (GPIOx_INT_EN)

R/W

000b

 

When set high the GPIOx are enabled as interrupt sources.

 

 

 

 

 

 

3

GP Timer Interrupt Enable (GPT_INT_EN)

R/W

0b

 

When set high the General Purpose Timer is enabled as an interrupt

 

 

 

source.

 

 

 

 

 

 

2

PHY Interrupt Enable (PHY_INT_EN)

R/W

0b

 

When set high, the PHY interrupt is enabled as an interrupt source.

 

 

 

 

 

 

1

Wake Event Interrupt Enable (WAKE_INT_EN)

R/W

0b

 

When set high, wake event detection is enabled as an interrupt source.

 

 

 

 

 

 

0

RESERVED

RO

-

 

 

 

 

Revision 1.22 (09-25-08)

88

SMSC LAN9420/LAN9420i

 

DATASHEET