Datasheet
4.2.3Interrupt Status Register (INT_STS)Offset: | 00C8h | Size: | 32 bits |
This register contains the current status of the generated interrupts. Some of these interrupts are also cleared through this register.
BITS | DESCRIPTION | TYPE | DEFAULT |
|
|
|
|
31:16 | RESERVED | RO | - |
|
|
|
|
15 | Software Interrupt (SW_INT) | R/WC | 0b |
| This bit latches high upon the SW_INT_EN bit toggling from a 0 to 1. The |
|
|
| interrupt is cleared by writing a ‘1’. Writing ‘0’ has no effect. |
|
|
|
|
|
|
14 | RESERVED | RO | - |
|
|
|
|
13 | Master Bus Error Interrupt (MBERR_INT) | R/WC | 0b |
| When set, indicates DMA Controller has detected an error during descriptor |
|
|
| read, or during a transmit data read operation. The interrupt is cleared by |
|
|
| writing a ‘1’ to this bit. Writing a ‘0’ has no effect. |
|
|
| To guarantee a clean recovery from a MBERR_INT condition, a software |
|
|
| reset must be performed by setting the Software Reset (SRST) bit of the |
|
|
| Bus Mode Register (BUS_MODE). Alternatively, the condition may be |
|
|
| cleared by a hardware reset. |
|
|
|
|
|
|
12 | Slave Bus Error Interrupt (SBERR_INT) | R/WC | 0b |
| When set, indicates that the PCI Target Interface has detected an error |
|
|
| when the Host attempted to access the LAN9420/LAN9420i CSR. The |
|
|
| interrupt is cleared by writing a ‘1’ to this bit. Writing a ‘0’ has no effect. |
|
|
| To guarantee a clean recovery from a SBERR_INT condition, a software |
|
|
| reset must be performed by setting the Software Reset (SRST) bit of the |
|
|
| Bus Mode Register (BUS_MODE). Alternatively, the condition may be |
|
|
| cleared by a hardware reset |
|
|
|
|
|
|
11:7 | RESERVED | RO | - |
|
|
|
|
6:4 | GPIO [2:0] (GPIOx_INT) | R/WC | 000b |
| Interrupts are generated from the GPIO’s. These interrupts are configured |
|
|
| through the GPIO_CFG register. Refer to 4.2.5, "General Purpose |
|
|
| Input/Output Configuration Register (GPIO_CFG)," on page 92 for more |
|
|
| information. These interrupts are cleared by writing a ‘1’ to the |
|
|
| corresponding bits. Writing ‘0’ has no effect. |
|
|
|
|
|
|
3 | GP Timer (GPT_INT) | R/WC | 0b |
| This interrupt is issued when the General Purpose Timer wraps from |
|
|
| maximum count to zero. This interrupt is cleared by writing a ‘1’ to this bit. |
|
|
| Writing ‘0’ has no effect. |
|
|
|
|
|
|
2 | PHY Interrupt (PHY_INT) | RO | 0b |
| Indicates assertion of the PHY Interrupt. The PHY interrupt is cleared by |
|
|
| clearing the interrupt source in the PHY Interrupt Status Register. Refer to |
|
|
| Section 4.5.11, "Interrupt Source Flag," on page 146 for more information |
|
|
| on this interrupt. Writing to this bit has no effect. |
|
|
|
|
|
|
SMSC LAN9420/LAN9420i | 89 | Revision 1.22 |
| DATASHEET |
|