SMSC LAN9420, LAN9420i MIN, TYP, MAX, Note, Note, UNITS, Note:, SYMBOL, DESCRIPTION, Table 5.11 PCI I/O Timing Values

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

Table 5.11 PCI I/O Timing Values

SYMBOL	DESCRIPTION	MIN	TYP	MAX	UNITS
tval	PCICLK to signal valid delay - bussed signals	2		11	ns
tval(nREQ)	PCICLK to nREQ signal valid delay (Note 5.15)	2		12	ns
ton	Float to active delay	2			ns
toff	Active to float delay			28	ns
tsu	Input setup time to PCICLK - bussed signals	7			ns
tsu(nGNT)	nGNT input setup time to PCICLK (Note 5.15)	10			ns
th	Input hold time from PCICLK	0			ns
trst	PCInRST active time after power stable	1			ms
	(Note 5.16)
trst-clk	PCInRST active time after PCICLK stable	100			us
	(Note 5.16)
trst-off	Rest active to output float delay (Note 5.16)			40	ns

Note: PCI signal timing is specified with loads detailed in Section 4.2.3.2 of the PCI Local Bus Specification, Rev. 3.0.

Note 5.15 nREQ and nGNT are point-to-point signals and have different timing characteristics than bussed signals. All other signals are bussed.

Note 5.16 PCInRST is asserted and deasserted asynchronously with respect to the PCICLK signal.

Revision 1.22 (09-25-08)	164	SMSC LAN9420/LAN9420i
	DATASHEET