Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

4.4.6MII Access Register (MII_ACCESS)

Offset:

0094h

Size:

32 bits

This register is used to control the management cycles to the internal PHY.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31-16

RESERVED

RO

-

 

 

 

 

15-11

PHY Address

R/W

00000b

 

For every access to this register, this field must be set to 00001b.

 

 

 

 

 

 

10-6

MII Register Index (MIIRINDA)

R/W

00000b

 

These bits select the desired MII register in the PHY.

 

 

 

 

 

 

5-2

RESERVED

RO

-

 

 

 

 

1

MII Write (MIIWnR)

R/W

0b

 

Setting this bit tells the PHY that this will be a write operation using the MII

 

 

 

data register. If this bit is not set, this will be a read operation, packing the

 

 

 

data in the MII data register.

 

 

 

 

 

 

0

MII Busy (MIIBZY)

R/W/SC

0b

 

This bit must be polled to determine when the MII register access is

 

 

 

complete. This bit must read a logical 0 before writing to this register or to

 

 

 

the MII data register. The LAN driver software must set (1) this bit in order

 

 

 

for the Host system to read or write any of the MII PHY registers.

 

 

 

During a MII register access, this bit will be set, signifying a read or write

 

 

 

access is in progress. The MII data register must be kept valid until the

 

 

 

MAC clears this bit during a PHY write operation. The MII data register is

 

 

 

invalid until the MAC has cleared this bit during a PHY read operation.

 

 

 

 

 

 

SMSC LAN9420/LAN9420i

127

Revision 1.22 (09-25-08)

 

DATASHEET