![](/images/backgrounds/136088/136088-16923x1.png)
Datasheet
Chapter 3 Functional Description
3.1Functional Overview
The LAN9420/LAN9420i Ethernet Controller consists of five major functional blocks. These blocks are:
The following sections discuss the features of each block. A block diagram of LAN9420/LAN9420i is shown in Figure 1.2 LAN9420/LAN9420i Internal Block Diagram on page 11.
3.2PCI Bridge (PCIB)
The PCI Bridge (PCIB) facilitates LAN9420/LAN9420i’s operation on a PCI bus as a device. It has the following features:
PCI Master Interface: This interface connects LAN9420/LAN9420i to the PCI bus when it is functioning as a PCI Master. It is used by the DMA engines to directly access the PCI Host’s memory.
PCI Target Interface: This interface connects LAN9420/LAN9420i to the PCI bus when it is functioning as a PCI Target. It provides access to PCI Configuration Space Control and Status Register (CONFIG CSR), and access to the Control and Status Registers (CSR) via I/O or
PCI Power Management Support: LAN9420/LAN9420i supports PCI Bus Power Management Interface Specification Rev. 1.1. Refer to Section 3.7, "Power Management," on page 73 for more information.
Interrupt Gating Logic: This logic controls assertion of the nINT signal to the Host system.
PCI Configuration Space Control and Status Registers (CONFIG CSR): The Host system controls and monitors the LAN9420/LAN9420i device using registers in this space.
SMSC LAN9420/LAN9420i | 23 | Revision 1.22 |
| DATASHEET |
|