Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

Note: For maximum power savings, auto-negotiation should be disabled before enabling the General Power-Down mode.

3.6.8.2Energy Detect Power-Down

This power-down mode is activated by setting the PHY register bit 17.13 to 1. Please refer to Section 4.5.8, "Mode Control/Status," on page 143 for additional information on this register. In this mode when no energy is present on the line, the PHY is powered down, with the exception of the management interface, the SQUELCH circuit and the ENERGYON logic. The ENERGYON logic is used to detect the presence of valid energy from 100BASE-TX, 10BASE-T, or Auto-negotiation signals

In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is transmitted. When energy is received - link pulses or packets - the internal ENERGYON signal is asserted, and the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts the INT7 bit of the PHY Interrupt Source Flag register. If the ENERGYON interrupt is enabled, this event will cause a PHY interrupt to the Interrupt Controller and the power management event detection logic.

The first and possibly the second packet to activate ENERGYON may be lost. When 17.13 is low, energy detect power-down is disabled.

3.6.9PHY Resets

In addition to a chip-level reset, the PHY supports two software-initiated resets. These are discussed in the following sections.

3.6.9.1PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)

The PHY soft reset is initiated by writing a ‘1’ to bit 10 of the PMT_CTRL register (PHY_RST). This self-clearing bit will return to ‘0’ after approximately 100μs, at which time the PHY reset is complete.

3.6.9.2PHY Soft Reset via PHY Basic Control Register bit 15 (PHY Reg. 0.15)

The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register. This self-clearing bit will return to ‘0’ after approximately 256μs, at which time the PHY reset is complete. The BCR reset initializes the logic within the PHY, with the exception of register bits marked as NASR (Not Affected by Software Reset).

3.6.10Required Ethernet Magnetics

The magnetics selected for use with LAN9420/LAN9420i should be an Auto-MDIX style magnetic available from several vendors. The user is urged to review SMSC Application Note 8.13 "Suggested Magnetics" for the latest qualified and suggested magnetics. Vendors and part numbers are provided in this application note.

3.6.11PHY Registers

Please refer to Section 4.5, "PHY Registers," on page 135 for a complete description of the PHY registers.

3.7Power Management

3.7.1Overview

LAN9420/LAN9420i supports the mandatory D0, D3H O T and D3COLD power states. LAN9420/LAN9420i can signal a wake event detection by asserting the nPME pin. The nPME signal can be generated in all states, including (optionally) the D3COLD state. LAN9420/LAN9420i can assert

SMSC LAN9420/LAN9420i

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Revision 1.22 (09-25-08)

 

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