Event Message | Severity | Cause |
|
|
|
Memory Removed (BANK# | Information | This event is generated when |
DIMM#) presence was |
| memory is removed from the |
asserted. |
| system. |
Memory Cfg Err | Critical | This event is generated when |
configuration error |
| memory configuration is |
(BANK# DIMM#) was |
| incorrect for the system. |
asserted. |
|
|
Mem Redun Gain redundancy | Information | This event is generated when |
regained. |
| memory redundancy is regained. |
Mem ECC Warning | Warning | This event is generated when |
transition to non- |
| correctable ECC errors have |
critical from OK. |
| increased from a normal rate. |
Mem ECC Warning | Critical | This event is generated when |
transition to critical |
| correctable ECC errors reach a |
from less severe. |
| critical rate. |
Mem CRC Err transition to | Critical | This event is generated when |
| CRC errors enter a non- | |
|
| recoverable state. |
|
|
|
Mem Fatal SB CRC | Critical | This event is generated while |
uncorrectable ECC was |
| storing CRC errors to memory. |
asserted. |
|
|
Mem Fatal NB CRC | Critical | This event is generated while |
uncorrectable ECC was |
| removing CRC errors from |
asserted. |
| memory. |
Mem Overtemp critical | Critical | This event is generated when |
over temperature was |
| system memory reaches critical |
asserted. |
| temperature. |
USB | Critical | This event is generated when the |
transition to non- |
| USB exceeds a predefined |
recoverable |
| current level. |
Hdwr version err hardware | Critical | This event is generated when |
incompatibility (BMC/ |
| there is a mismatch between the |
iDRAC Firmware and CPU |
| BMC and iDRAC firmware and |
mismatch) was asserted. |
| the processor in use or vice |
|
| versa. |
|
|
|
Hdwr version err hardware | Information | This event is generated when an |
incompatibility (BMC/ |
| earlier mismatch between the |
iDRAC Firmware and CPU |
| BMC and iDRAC firmware and |
mismatch) was deasserted. |
| the processor is corrected. |
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