SYSTEM MAINTENANCE OUTLINE

 

IMG2

 

PIM 3

PM BUS

 

MUX

 

 

LC/TRK

LC/TRK

 

 

MUX

 

PM BUS

PIM 2

PM BUS

 

MUX

 

 

LC/TRK

LC/TRK

 

 

MUX

 

PM BUS

PIM 1

PM BUS

 

MUX

 

 

LC/TRK

LC/TRK

 

 

MUX

 

PM BUS

PIM 0

PM BUS

 

MUX

 

 

LC/TRK

LC/TRK

 

 

MUX

 

PM BUS

 

IMG3

 

PIM 3

PM BUS

 

MUX

 

 

LC/TRK

LC/TRK

 

 

MUX

 

PM BUS

PIM 2

PM BUS

 

MUX

 

 

LC/TRK

LC/TRK

 

 

MUX

 

PM BUS

PIM 1

PM BUS

 

MUX

 

 

LC/TRK

LC/TRK

 

 

MUX

 

PM BUS

PIM 0

PM BUS

 

MUX

 

 

LC/TRK

LC/TRK

 

 

MUX

 

PM BUS

 

To IMG 0 To IMG 1

To IMG 0 To IMG 1

LPM

CPR Note 2

T

ISAGT 0

M

CPU clock

ISA BUS

PCI BUS CPU 0

TSWM

 

TSW

TSW

 

 

 

TSW

TSW

M M M M

M M M M

/INT

/INT

M M M M

M M M M

/INT

/INT

U U U U

U U U U

 

 

U U U U

U U U U

 

 

X X X X

X X X X

TSW

TSW

X X X X

X X X X

TSW

TSW

023 022 021 020

033 032 031030

120 121 122123

130 131 132 133

 

 

00

01

 

 

 

10

11

TSW/INT

TSW/INT

 

 

TSW/INT

TSW/INT

 

 

TSW 02

TSW 03

 

 

 

TSW 12

TSW 13

 

 

 

TSW I/O

BUS

 

 

 

TSW I/O

BUS

 

 

MISC BUS

 

 

 

 

MISC BUS

 

 

 

DLKC 0

 

 

 

 

DLKC 1

 

 

IOP1

MISC BUS

 

 

 

 

MISC BUS

 

 

GT 0

 

MISC BUS

 

 

 

 

 

 

 

 

 

 

 

 

Note 3

 

Note 1

 

 

 

 

 

 

 

 

PLO 0

PLO 1

 

 

GT 1

 

MISC BUS

 

 

 

 

 

 

 

 

 

 

 

 

 

IOP0

 

 

 

 

 

 

 

 

 

Symbols

 

 

 

 

 

 

MISC BUS

: Controlling Routes of CPU

: Cable

 

 

: Circuit card (active)

: Circuit card (STBY)

LANI MEMORY

Reset Signal

EMA

IOC /

 

: External Cable

: Clock Oscillator

MISC

CPR

: Signral

 

 

 

 

 

 

 

 

(ST-BY)

 

 

CPU board

PWR

 

MISC BUS

 

T

EMA:

PH-PC40

ISAGT:

PZ-GT13

 

ISAGT 1

 

 

LANI:

PZ-PC19

GT:

PH-GT09

 

 

 

 

 

 

 

 

 

 

 

 

 

IOC:

PH-IO24

TSW:

PH-SW12

PWR

 

 

 

 

 

 

 

 

DLKC:

PH-PC20

PLO:

PH-CK16/17/16-A/17-A

 

 

 

 

 

MUX:

PH-PC36

 

 

Note 1: The circuit cards, drawn by dotted lines, indicate they are in STBY state. These cards (TSW, MUX and DLKC) are totally changed over to the ACT mode, when the MBR key of the active GT (PH-GT09) card is once flipped. However, PLO (PH-CK16/17/16-A/17-A) is independent and not affected by the development.

Note 2: If the ACT/STBY of CPU is once changed over, the system of GT (in TSWM) also changes over.

Note 3: Though an external cable is physically connected between ISAGT0 and GT1, the actual control signal is sent/received only between ISAGT0 and GT0. This is because GT0 and GT1 are having a multiple connection on the backboard side. (Refer to Chapter 6, Section 12.)

Figure 2-16 CPU Controlling Block Diagram (Continued)

NDA-24300CHAPTER 2

Page 21

Issue 1

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Image 48
NEC NDA-24300 manual IMG2