Teledyne M300E Notes, This schematic is based on, applies to PCA PN, the PWB PN, 03974 and

D

C

B

A

1

2

3

4

M1

M2

VCC

20

U1

M3

M4

S8

1

Vcc

D_A

19

18

2

Y1

D_B

17

Y2

D_C

3

16

Y3

D_D

4

15

S7

Y4

D_E

M6

M5

5

VCC

Y5

6

13

OSC

AVL

7

C1

KBM

KEYBOARD, LED & HORN

12

S6

X1

.1uF + C6

14

11

24

U2

OE

X2

9

Vdd

Vss

X4

KBD_A0

21 A0

P00

4

8

10uF

X3

M7

S5

KBD_A1

2

A1

P01

5

74C923

10

KBD_A2

3

6

A2

P02

1

7

INT

P03

8

SCL

P04

MAINT_SW

S4

22

9

SCL

P05

SDA

23

10

LANG_SELCT

SDA

P06

M9

M8

11

P07

GRN LED

13

P10

14

YEL LED

S3

PCF8575 P11

15

RED LED

P12

16

LED 4

P13

M10

17

LED 5

MF3

VCC

P14

S2

VCC

18

LED 6

R2

P15

U3A

19

HORN

P16

1.0K

4

20

SPR_I/O_0

1

PRE

P17

3

Q

5

Vss

CLK

MF4

S1

RN1

2

D

Q

6

4.7K

1

12

CLR

C7

2 3 4 5 6

300pF

MM74HC74A

VCC

S9

RI-1000 ONLY

U4

16

OPT. MAINT SWITCH

VCC

DISP_DA_A0

Vdd

1

AO

P0

4

S12

U3B

DISP_DA_A1

2

5

A1

P1

10

DISP_DA_A2

3

6

PRE

KYBRD_INT

A2

P2

11

9

7

J4

VCC

1

CLK

Q

SCL

P3

T8201

12

8

14

9

RN5

D

Q

SCL

P4

MAINT SW

MAINT_SW

13

SDA

15

10

1

CLR

SDA

P5

MAINT SW RET

4.7K

11

2

P6

MAINT LED V+

MAINT_LED_V+

MM74HC74A

PCF8574

12

3

P7

MAINT LED

MAINT_LED

2 3 4 5 6 7 8 9 10

4

LANG SW

LANG_SELCT

KBD_A0

DISPLAY DATA

13

5

INT

LANG SW RET

KBD_A1

Vss

6

SPR I/O_0

SPR_I/O_0

KBD_A2

DISP_DA_A0

JP2 I2C TERMINATION

7

SPR I/O RET

DISP_CN_A0

DISP_DA_A1

SCL

8

8

1

2

SPR I/O_1

SPR_I/O_1

DISP_CN_A1

DISP_DA_A2

SDA

9

3

4

SPR I/O RET

DISP_CN_A2

DISP_PWR_EN must

10

SPR I/O_2

SPR_I/O_2

11

be high for display to

SPR I/O RET

DEFAULT ADDRESS SELECTS FOR I2C TO PARALLEL

12

OPT. LANG. SWITCH

JP1

be powered.

VCC

13

DECODERS:

ADRS SLCTS

14

KEYBOARD (KBD_A0 - A2)

S13

1 3 5 7 9

11 13 15 17

3M-2514-6002UB

16

1 1 1

DISPLAY CONTROL

DISPL CONTROL (DISP_CN_A0 -A1)

U5

2 4 6 8 10

12

14 16 18

0 1 1

Vdd

GND

VCC

+5_DISP

SDA

KYBRD INT

DISP_CN_A0

1

AO

P0

4

DISP_CN_A1

2

5

A1

P1

TP1

TP2

TP3

TP4

TP5

NOTES:

DISP_CN_A2

3

6

A2

P2

SDA

KYBRD_INT

7

VCC

+5_DISP

1. This schematic is based on

SCL

P3

14

9

SCL

P4

DISP_PWR

DISP_RET

BUSY

SCL

R3

the PWB PN, 03974 and

SDA

15

10

SDA

P5

applies to PCA PN, 03975

11

TP6

TP7

TP8

TP9

4.7K

R4

P6

12

DISP_BUSY

SCL

P7

DISP_PWR

DISP_RET

4.7K

13

INT

+5_DISP

Vss

VCC

(U1)

(U2)

(U4)

(U45

1

6

SCL

1

6

SCL

DISP_RET

PCF8574

8

+5_DISP

+5_DISP

2

7

KYBRD_INT

2

7

KYBRD_INT

VCC

3

8

DISP_RET

VCC

3

8

DISP_RET

C11

C12

C10

+ C14

C4

C9

C8

+ C13

C2

C3

C5

C15

C16

4

9

4

9

SDA 5

10

SDA

5

10

220pF

220pF

220pF

100uF

.1uF

220pF

220pF

10uF

.1uF

.1uF

.1uF

.1uF

.1uF

J1

JP3

J2

JP4

DISP_RET

1 2 3 4

		5		6
		VCC
DS1	GRN		RN3
		1	10	MAINT_LED_V+
DS2		2	9
	YEL	3	8	D
		4	7
		5	6
DS3	RED

220

DS4

+

DS5

DS6

RI-1000 ONLY

Layout Instructions:

A1

1. Minimum trace width 8 mil would like to have

SONALERT

10 mil traces if possible.

2. Please run traces on both and backside but

where possible fill one side with GND.

3. Minimum width for +5_DISP, DISP_PWR,

C

DISP_RET is 40 mil, except to test points.

4. Minimum width for VCC, GND, Vdd, Vss is

30 mil, except to test points

J3 TO/FRM DISPLAY

2

1

4

3

6

5

8

7

DISP_WR

10

9

DISP_BUSY

12

11

14

13

16

15

DISP_RET

DISP_PWR

+5_DISP

VCC

B

C17

1

1

Q1

6

+5_DISP

RN2

D

2

5

1500uF

4.7K

3

4

G

S

2 3 4 5 6

SI3443DV

DISP_WR

JP5

DISP_PWR_OVR

DISP_BUSY

DISP_PWR_EN

1

MAINT_LED

MCP120T

2

1

Vdd

RST

3

MMBT3904

Q2

U6

Vss

R20

2

1K

4.85V DTCT

SPR_I/O_1

SPR_I/O_2

A

Title

Schematic for PCA #04258 and PCB #04257, Keyboard/Display Interface for E series

Size

Number

04259

Revision

B

a

Date:

21-Mar-2002

Sheet of

File:

N:\YHWork\M300B\keyboard\04257a\04259A.ddbDrawn By:

5

6