Teledyne M300E Notes, This schematic is based on the, PWB PN, 03974 and applies to, Pca Pn

D

C

B

A

1

2

3

4

M1

M2

VCC

20

U1

M3

M4

S8

1

Vcc

D_A

19

18

2

Y1

D_B

17

Y2

D_C

3

16

Y3

D_D

4

15

S7

Y4

D_E

M6

M5

5

VCC

Y5

6

13

OSC

AVL

7

C1

KBM

KEYBOARD, LED & HORN

S6

X1

12

.1uF

+ C6

14

11

24

U2

OE

X2

9

Vdd

10uF

Vss

X4

KBD_A0

21

A0

P00

4

8

X3

M7

S5

KBD_A1

2

A1

P01

5

74C923

KBD_A2

3

6

10

A2

P02

1

7

INT

P03

8

SCL

P04

MAINT_SW

S4

22

9

SCL

P05

SDA

23

10

LANG_SELCT

SDA

P06

M9

M8

11

P07

GRN LED

13

P10

PCF8575

14

YEL LED

S3

P11

15

RED LED

P12

16

LED 4

P13

M10

17

LED 5

MF3

VCC

P14

VCC

18

LED 6

S2

P15

R2

U3A

19

HORN

P16

1.0K

4

20

SPR_I/O_0

1

PRE

P17

3

5

Vss

CLK

Q

MF4

RN1

2

6

S1

D

Q

4.7K

1

CLR

12

C7

2 3 4 5 6

300pF

MM74HC74A

VCC

S9

RI-1000 ONLY

U4

16

VCC

OPT. MAINT SWITCH

DISP_DA_A0

Vdd

1

AO

P0

4

S12

U3B

DISP_DA_A1

2

5

A1

P1

10

DISP_DA_A2

3

6

PRE

A2

P2

11

9

KYBRD_INT

7

J4

VCC

1

CLK

Q

SCL

P3

T8201

12

8

14

9

RN5

D

Q

SCL

P4

MAINT SW

13

SDA

15

10

1

MAINT_SW

CLR

SDA

P5

MAINT SW RET

4.7K

11

2

P6

MAINT LED V+

MAINT_LED_V+

MM74HC74A

12

3

PCF8574

P7

MAINT LED

MAINT_LED

2 3 4 5 6 7 8 9

4

10

LANG SW

LANG_SELCT

KBD_A0

DISPLAY DATA

13

5

INT

LANG SW RET

KBD_A1

Vss

6

SPR I/O_0

SPR_I/O_0

KBD_A2

DISP_DA_A0

JP2 I2C TERMINATION

7

SPR I/O RET

DISP_CN_A0

DISP_DA_A1

SCL

8

8

1

2

SPR I/O_1

SPR_I/O_1

DISP_CN_A1

DISP_DA_A2

SDA

9

3

4

SPR I/O RET

DISP_CN_A2

DISP_PWR_EN must be

10

SPR I/O_2

SPR_I/O_2

11

high for display to be

SPR I/O RET

12

OPT. LANG. SWITCH

JP1

DEFAULT ADDRESS SELECTS FOR I2C TO PARALLEL

powered.

VCC

13

DECODERS:

ADRS SLCTS

14

KEYBOARD (KBD_A0 - A2)

S13

1 3 5 7 9

11 13 15 17

3M-2514-6002UB

1 1 1

16

DISPLAY CONTROL

DISPL CONTROL (DISP_CN_A0 -A1)

U5

2 4 6 8 10 12 14 16 18

0 1 1

Vdd

GND

VCC

+5_DISP

SDA

KYBRD INT

DISP_CN_A0

1

AO

P0

4

DISP_CN_A1

2

5

A1

P1

TP1

TP2

TP3

TP4

TP5

NOTES:

DISP_CN_A2

3

6

SDA

KYBRD_INT

A2

P2

7

VCC

+5_DISP

1. This schematic is based on the

SCL

P3

14

9

PWB PN, 03974 and applies to

SCL

P4

DISP_PWR

DISP_RET

BUSY

SCL

R3

SDA

15

10

PCA PN, 03975

SDA

P5

11

TP6

TP7

TP8

TP9

4.7K

R4

P6

12

DISP_PWR

DISP_RET

DISP_BUSY

SCL

4.7K

P7

13

INT

+5_DISP

Vss

VCC

(U1)

(U2)

(U4)

(U45

+5_DISP

1

6

SCL

+5_DISP

1

6

SCL

DISP_RET

PCF8574

8

2

7

KYBRD_INT

2

7

KYBRD_INT

VCC

3

8

DISP_RET

VCC

3

8

DISP_RET

C11

C12

C10

+

C14

C4

C9

C8

+ C13

C2

C3

C5

C15

C16

4

9

4

9

SDA

5

10

SDA

5

10

220pF

220pF

220pF

100uF

.1uF

220pF

220pF

10uF

.1uF

.1uF

.1uF

.1uF

.1uF

J1

JP3

J2

JP4

DISP_RET

1 2 3 4

		5		6
		VCC
DS1	GRN		RN3
		1	10	MAINT_LED_V+
		2	9
DS2	YEL	3	8
		4	7	D
		5	6
DS3	RED		220

DS4

+

DS5

DS6

RI-1000 ONLY

				Layout Instructions:
		A1		1. Minimum trace width 8 mil would like to have 10
		SONALERT		mil traces if possible.
				2. Please run traces on both and backside but where
				possible fill one side with GND.
				3. Minimum width for +5_DISP, DISP_PWR,			C
				DISP_RET is 40 mil, except to test points.
				4. Minimum width for VCC, GND, Vdd, Vss is 30
				mil, except to test points
		J3 TO/FRM DISPLAY
		2	1
		4	3
		6	5
		8	7	DISP_WR
		10	9
				DISP_BUSY
		12	11
		14	13
		16	15
						DISP_PWR
+5_DISP				DISP_RET
		VCC					B
C17		1		1	Q1	+5_DISP
		RN2			D	6
				2		5
1500uF		4.7K
				3		4
					G
						S
		2 3 4 5 6			SI3443DV
DISP_WR						JP5
						DISP_PWR_OVR
DISP_BUSY
DISP_PWR_EN						1
MAINT_LED	MCP120T
						2
1	Vdd	3		MMBT3904
		RST			Q2
U6		Vss	R20
	2		1K
4.85V DTCT
SPR_I/O_1
SPR_I/O_2
							A
Title		Keyboard/Display Interface
Size		Number			Revision
B		03976				B
Date:		15-Mar-2002		Sheet of
File:		N:\PCBMGR\RELEASED\03975yh\Protel\03975bDrawn.ddbBy:
5					6