Teledyne M300EM operation manual Sync/Demod Status LED’s, Photo-DetectorTemperature Control

Theory of Operation Teledyne API – Technical Manual - Model 300E Family CO Analyzers

Timing for activating the Sample and Hold Circuits is provided by a Phase Lock Loop (PLL) circuit. Using the segment sensor output as a reference signal the PLL generates clock signal at ten times that frequency. This faster clock signal is used by the PLD to make the Sample and Hold Circuits capture the signal during the center portions of the detected waveform, ignore the rising and falling edges of the detector signal.

Sample & Hold

Active

Detector

Output

Sample & Hold

Inactive

Figure 11-13: Sample & Hold Timing

11.5.4.3.Sync/Demod Status LED’s

The following two status LED’s located on the sync/demod board provide additional diagnostic tools for checking the GFC Wheel rotation.

Table 11-3: Sync/Demod Status LED Activity

LED	Function	Status OK
D1	M/R Sensor Status	LED flashes approximately
		2/second
D2	Segment Sensor	LED flashes approximately
	Status	6/second

See Section 13.1.4.2 for more information.

Fault Status

LED is stuck ON or OFF

LED is stuck ON or OFF

11.5.4.4.Photo-Detector Temperature Control

The sync/demod board also contains circuitry that controls the IR photo-detector’s Thermal Electric Coolers (TEC). A drive voltage, PHT DRIVE, is supplied to the coolers by the sync/demod board which is adjusted by the sync/demod board based on a return signal called TEC control which alerts the sync/demod board of the detector’s temperature. The warmer the detector, the harder the coolers are driven.

PHT DRIVE is one of the Test Functions viewable by the user via the form panel. Press <TST or TST> until it appears on the display.

11.5.4.5.Dark Calibration Switch

This switch initiates the Dark Calibration procedure. When initiated by the user (See Section 9.6.1 for more details), the dark calibration process opens this switch, interrupting the signal from the IR photo-detector. This allows the analyzer to measure any offset caused by the sync/demod board circuitry.

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