Intel 460GX manuals
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294 pages 2.76 Mb
3 Contents13 Introduction21 Register Descriptions2.1Access Mechanism 22 2.2Access Restrictions23 2.2.2Register Attributes2.2.3Reserved Bits Defined in Registers 2.2.4Reserved or Undefined Register Locations 2.2.5Default Upon Reset 24 2.3I/O Mapped Registers25 2.4Error Handling Registers26 7Disable6Valid ITID DEDTID: DED ITID FSETID: FSE ITID 27 2.4.1.4FERR_SAC: First Error Status Register31Memory Card B Error (MBE) 30Memory Card A Error (MAE) 29XSERR# Asserted (XSA) 28‘Store-Write’Command Underflow, card A, Stack L (SCAL) 27‘Store-Write’Command Underflow, card A, Stack R (SCAR) 26‘Store-Write’Command Underflow, card B, Stack L (SCBL) 25‘Store-Write’Command Underflow, card B, Stack R (SCBR) 24SDC Correctable Memory Error (SCME) 23SDC Non-FatalError (SNE) 22SDC Fatal Error (SFE) Fatal error in SDC 21‘Completion’ Command Underflow; MAC A, Stack L (CCAL) 20‘Completion’ Command Underflow; MAC A, Stack R (CCAR) 19‘Completion’ Command Underflow; MAC B, Stack L (CCBL) 28 18‘Completion’ Command Underflow; MAC B, Stack R (CCBR)17BERR# Observed (BER) 16IOQ Underflow/Overflow (IUE) 15reserved(0) 14External XBINIT# Active. (XBE) 13False Retirement (FRE) 12Address above TOM (TE) 11Illegal HITM# (IHS) 10Unsupported ASZ[1:0]# (ASE) 9System Bus Address Parity Error (AE) Parity error on A[36:3]# 8System Bus Request Parity Error (RQE) Parity error on REQ[4:0]# 7PDB ITID Parity Error (IPE) 6Retirement Bus Parity Error (RPE) 5Lock# Transaction With No Resources Available (LTE) 0Resource Counter Overflow/Underflow (RCE) 2.4.1.5NERR_SAC: All Error Status Register 31:0 See FERR_SAC for bit definitions 29 2.4.1.6SA_FERR: System Address on First Error106LOCK, ’b’ phase 105ADS, ’b’ phase 104RP#, ’b’ phase. 103:99 REQ, ’b’ phase 98AP1; ’b’ phase 97AP0; ’b’ phase 96:64 A[35:3]#, ’b’ phase 42LOCK#, ’a’ phase 41ADS#, ’a’ phase 40RP# for REQa# REQa# 34:33 AP[1:0]#, ’a’ phase 32:0 Aa[35:3]#, ’a’ phase 2.4.1.7BIUITID: BIU ITID Register 30 2.4.1.8BIUDATA: BIU Data Register115:82 Address bits [35:2] Reqa DID BE OWN DPS Reqb Lock LockLoad Dst ORetry CMD FEorR FRoute FLEN FTID Len System Bus Retry Dfr MEM System Bus CLINE Zero RS 31 2.4.2SDC2.4.2.1SEC0_D_FERR: Data on First Memory Card B SEC 2.4.2.2SEC0_ECC_FERR: ECC on First Memory Card B SEC 2.4.2.3SEC0_TXINFO_FERR: TXINFO on First Memory Card B SEC 32 2.4.2.4DED0_D_FERR: Data on First Memory Card B DED2.4.2.5DED0_ECC_FERR: ECC on First Memory Card B DED 2.4.2.6DED0_TXINFO_FERR: TXINFO on First Memory Card B DED 2.4.2.7SEC1_D_FERR: Data on First Memory Card A SEC 33 2.4.2.8SEC1_ECC_FERR: ECC on First Memory Card A SEC2.4.2.9SEC1_TXINFO_FERR: TXINFO on First Memory Card A SEC 2.4.2.10DED1_D_FERR: Data on First Memory Card A DED 34 2.4.2.11DED1_ECC_FERR: ECC on First Memory Card A DED2.4.2.12DED1_TXINFO_FERR: TXINFO on First Memory Card A DED 2.4.2.13SDC_FERR: First Error Status Register 30PDB Receive Length Error (RLE) Private Bus receive length error 29DRDY# Protocol Error (FS2) 28Write Data Protocol Error (FS1) Asserted on write protocol errors 27LEN# Protocol Error (FS0) 35 26’Forward’ Overlapping ’Forward’; Card A (FWMDI1)25’Load’ Overlapping ’Load’; Card A (LRMDI1) 24’Load’ Overlapping ’Forward’; Card A (WrRd1) 23’Forward’ Overlapping ’Load’; Card A (RdWr1) 22’Forward’ Underflow; Card A Right Stack Error (FR1) 21’Forward’ Underflow; Card A Left Stack Error (FL1) 20’Accept Underflow’; Card A (AE1) 19’Forward’ Overlapping ’Forward’; Card B (FWMDI0) 18’Load’ Overlapping ’Load’; Card B (LRMDI0) 17’Load’ Overlapping ’Forward’; Card B (WrRd0) 16’Forward’ Overlapping ’Load’; Card B (RdWr0) 15’Forward’ Underflow; Card B Right Stack Error (FR0) 14’Forward’ Underflow; Card B Left Stack Error (FL0) 13’Accept’ Underflow; Card B (AE0) 12Configuration Information Parity Error (CIE) 11Response Bus Transmission Error (RTE) 10PDB - ITID Parity Error (IPE) 9PDB - Command Parity Error (CPE) Look in CMD_FERR Register to isolate 8PDB Byte Enable Parity Error (BPE) 7SDC Data Buffer RAM Parity Error (RPE) 6PDB - Data Parity Error (DPE) 36 5System Bus Double Bit Error (DEDF)4System Bus Single Bit Error (SECF) 3SDC Card A Double Bit Error (DED1) 2SDC Card A Single Bit Error (SEC1) 1SDC Card B Double Bit Error (DED0) 0SDC Card B Single Bit Error (SEC0) 2.4.2.14SDC_NERR: SDC Next Error Status Register 2.4.2.15PCMD_FERR: Command on First PCMD Parity Error 2.4.2.16PITID_FERR: Data on First PITID Parity Error 37 2.4.2.17SDCRSP_FERR: Response on First SDCRSP Error2.4.2.18DPBRLE_FERR: Private Data Bus Receive Length Error 2.4.2.19ECCMSK0: ECC Mask Register - Card B 38 ECC Generation Mask2.4.2.20ECCMSK1: ECC Mask Register - Card A 2.4.2.21ECCMSKF: ECC Mask Register 2.4.2.22ParMskP: PB Parity Mask and IB Correction Enable Register 39 2.4.2.23PVD_D_FERR: Data on First PVD Parity Error2.4.2.24PVD_PAR_FERR: Parity on First PVD Parity Error 2.4.2.25PVD_TXINFO_FERR: TXINFO on First PVD Parity Error 40 2.4.2.26SECF_D_FERR: Data on First System Bus SEC2.4.2.27SECF_ECC_FERR: ECC on First System Bus SEC 2.4.2.28SECF_TXINFO_FERR: TXINFO on First System Bus SEC 2.4.2.29DEDF_D_FERR: Data on First System Bus DED 2.4.2.30DEDF_ECC_FERR: ECC on First System Bus DED 2.4.2.31DEDF_TXINFO_FERR: TXINFO on First System Bus DED 41 2.4.3MAC2.4.3.1FERR_MAC: First Error Status Register 1Que-OverflowError 0Parity Error - CMND 2.4.3.2CMND_FERR: Command on First Error 42 2.4.4PXB2.4.4.1ERRSTS: Error Status Register 6PERR# observed on PCI Bus 5Parity Error on Received PCI Data 4Parity Error on PCI Address 43 3Inbound Delayed Read Time-outFlag1Performance Monitor #1 Event Flag 0Performance Monitor #0 Event Flag 2.4.4.2ERRCMD: Error Command Register 6Assert SERR# on Observed Parity Error 5Assert SERR# on Received Data with Parity Error 4Assert SERR# on Address Parity Error 3Assert PERR# on Data Parity Error 2Assert SERR# on Inbound Delayed Read Time-out 0Return Hard Fail Upon Generating Master Abort 44 2.4.5GXBFERR_GXB 2FERR_PCI bit asserted 1FERR_AGP bit asserted 0 FERR_GART bit asserted 2.4.5.2FERR_PCI 7PCISTS Error Logged 6Non-ConfigurationMaster Abort 5Discard Timer Expiration This is the 215 clock timeout 4SERR# Observed 3PERR# Observed 2PCI Inbound Read Que Data Parity Error 1PCI Outbound Write Que Data Parity Error 0Illegal OB GART Access 2.4.5.3FERR_AGP: First Error Status Register for AGP 45 5Lo-priorityRead Data Que Parity Error4Hi-priorityRead Data Que Parity Error 3Use of Pipe with Sideband Enabled 2AGP address from graphics card [63:40] not equal to 1AGP Request Queue Overflow 0 Illegal AGP Command 2.4.5.4FERR_GART: First Error Status Register for GART 3GART Parity Error 2GART Entry Invalid Illegal Address 2.4.5.5NERR_AGP: Next Errors Status Register for AGP 46 2.4.5.6NERR_GART2.4.5.7PAC_ERR: PCI Address & Cmd First Error PCI Command PCI Address 2.4.5.8PD_ERR: PCI Data First Error PCI Byte Enable [3:0] PCI Data 47 2.4.6WXB2.4.6.1ERRSTS: Error Status Register power-good 7INTRQ Asserted Flag 6XBINIT Asserted Flag 5NEPCI Register Records an PCI Bus Error Flag not 3FEPCI Register Records an PCI Bus Error Flag 48 2.4.6.2ERRCMD: Error Command Register15XBINITO: XBinit Override Enable 13IRQE: INTRQ Enable 12ASAPE: Assert SERR# on Address Parity Error 11ASDPE: Assert SERR# on any Data Parity Error 10ASDTE: Assert SERR# on Discard Timer Expiration 2.4.6.3FEPCI: PCI Bus First Error Status Register 49 7PCILV: PCI Error Logs Valid6UMATA: Unexpected Master or Target Abort 5DTE: Discard Timer Expiration 4SES: System Error Signaled 3PODT: PERR# Observed on PCI Data Transfer 1PEOD: Parity Error on Received PCI Data 0PEPA: Parity Error on PCI Address 2.4.6.4NEPCI: PCI Bus Next Error Status Register 50 2.5Performance Monitor Registers51 39Overflow38:0 Count Value IT_MON_PMC_[0 to 5]: Internal Transaction Performance Monitor Config. Register 40:33 Length Encodings 32:24 DMASK Encodings 52 23:15 UMASK Encodings14:8 Event Select 53 6:5 Disable Source4:3 Enable Source 2:0 Reload Control 54 2.5.2SDC2.5.2.1FSB_D_PMC_[1,0]: System Bus Performance Monitor Configuration Register Mask 14:8 Event Select 6:5 Disable Source 55 4:3 Enable Source2:0 Reload Control 2.5.2.2FSB_D_PMD_[1,0]: System Bus Performance Monitor Data Registers 56 2.5.3PXB2.5.3.1PMD[1:0]: Performance Monitoring Data Register 31:0 Count Value 2.5.3.2PMR[1:0]: Performance Monitoring Response 7:6 Interrupt Assertion 5:4 Performance Monitoring pin assertion 3:2 Count Mode 57 1:0 Reload Mode2.5.3.3PME[1:0]: Performance Monitoring Event Selection 14Count Data Cycles 13:10 Initiating Agent Selection 9:8 Transaction Destination Selection 5:0 Event Selection Individual Bus Transactions Generic (Grouped) Bus Transactions Bus Signal Assertions 58 2.5.4GXB2.5.4.1AGP_PMD_0,1: AGP Performance Monitor Data Registers 59 2.5.4.2PCI_PMD: PCI Performance Monitor Data Registers2.5.4.3PERCON: Performance Monitor Control Register 1Event 1 Input 60 0Event 0 Input2.5.4.4AGP_PMC_[0,1]: AGP Performance Monitor Configuration Register QW (8 bytes). Used also for code 11 0000 00 - All events 17:16 Pipe or Sideband Request Mask 13:8 Event Select 61 7EVENT1 Count Enable2.5.4.5PCI_PMC: PCI Performance Monitor Configuration Register 17:16 Initiating Agent 63 2.5.5WXB2.5.5.1PCI_WXB_PMC0: PCI Performance Monitor Configuration Register 23:21 Data Transfer and Transaction Qualifier 18:17 Issuing Agent Qualifier 16:11 Event Select Measurement Transaction Types 3Enable Source 64 2.6Interrupt Related Registers65 2.6.2PID PCI Memory-mappedRegistersTable 2-2. Memory-MappedRegister Summary 2.6.2.1I/O Register Select Register (FEC00000h) Table 2-3.I/O Select Register Format 2.6.2.2I/O Window Register (FEC00010h) Table 2-4.I/O Window Register Format 2.6.2.3(x)APIC EOI Register (FEC00040h) Table 2-5.(x)APIC EOI Register Format 66 2.6.3PID Indirect Access Registers73 System Architecture81 System Address Map91 Memory Subsystem99 Data Integrity and Error Handling131 AGP Subsystem147 WXB Hot-Plug165 IFB Register Mapping171 IFB Usage Considerations191 LPC/FWH Interface Configuration233 IDE Configuration245 Universal Serial Bus (USB)Configuration 259 SM Bus Controller Configuration271 PCI/LPC Bridge Description289 IFB Power Management
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