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NXP Semiconductors UM10237 User Manual
792 pages 4.45 Mb
UM10237LPC24XX User manualRev. 02 19 December 2008 User manual 2 Contact information1. Introduction 2. How to read this manual 3 UM10237Chapter 1: LPC24XX Introductory information 4 3. LPC2400 features6 5. Ordering options5.1 LPC2458 ordering options 5.2 LPC2460 ordering options 7 NXP Semiconductors UM102375.3 LPC2468 ordering options 5.4 LPC2470 ordering options 5.5 LPC2478 ordering options 8 6. Architectural overview9 7. On-chip flash programming memory (LPC2458/68/78)NXP Semiconductors UM10237 10 8. On-chip SRAM11 9. LPC2458 block diagramFig 1. LPC2458 block diagram 12 10. LPC2420/60 block diagram(1) LPC2460 only. Fig 2. LPC2460 block diagram 13 11. LPC2468 block diagramFig 3. LPC2468 block diagram 14 12. LPC2470 block diagramFig 4. LPC2470 block diagram 15 13. LPC2478 block diagramFig 5. LPC2478 block diagram 16 2. Memory map and peripheral addressingChapter 2: LPC24XX Memory mapping 18 3. Memory maps22 4. APB peripheral addressesNXP Semiconductors UM10237 23 5. LPC2400 memory re-mapping and boot ROM25 6. Memory mapping control6.1 Memory Mapping Control Register (MEMMAP - 0xE01F C040) 6.2 Memory mapping control usage notes 27 7. Prefetch abort and data abort exceptions28 1. Summary of system control block functions2. Pin descriptionChapter 3: LPC24XX System control 40 4. Brown-out detection5. Code security vs. debugging 41 1. Summary of clocking and power control functionsChapter 4: LPC24XX Clocking and power control 43 2. Oscillators2.1 Internal RC oscillator 2.2 Main oscillator 45 2.3 RTC oscillator3.1 Clock source selection multiplexer 46 3.1.1 Clock Source Select register (CLKSRCSEL - 0xE01F C10C) 3.2 PLL (Phase Locked Loop) 53 3.2.12 Procedure for determining PLL settings 3.2.13 Examples of PLL settings 54 55 3.2.14 PLL setup sequence 56 3.3 Clock dividers59 3.4 Power control65 4. Power domains5. Wakeup timer 68 5. EMC functional description69 5.1 AHB slave register interface 70 5.2 AHB slave memory interface5.2.1 Memory transaction endianness 5.2.2 Memory transaction size 5.2.3 Write protected memory areas 5.3 Pad interface 5.4 Data buffers 71 6. Low-power operation6.1 Low-power SDRAM Deep-sleep Mode 6.2 Low-power SDRAM partial array refresh 72 7. Memory bank select73 8. Reset9. Pin description 74 10. Register description76 10.1 EMC Control register (EMCControl - 0xFFE0 8000)77 10.2 EMC Status register (EMCStatus - 0xFFE0 8004)78 10.3 EMC Configuration register (EMCConfig - 0xFFE0 8008)10.4 Dynamic Memory Control register (EMCDynamicControl - 0xFFE0 8020) 80 10.5 Dynamic Memory Refresh Timer register (EMCDynamicRefresh - 0xFFE0 8024)81 10.6 Dynamic Memory Read Configuration register (EMCDynamicReadConfig - 0xFFE0 8028)10.7 Dynamic Memory Percentage Command Period register (EMCDynamictRP - 0xFFE0 8030) 82 10.8 Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS - 0xFFE0 8034)10.9 Dynamic Memory Self-refresh Exit Time register (EMCDynamictSREX - 0xFFE0 8038) 83 10.10 Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR - 0xFFE0 803C)10.11 Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL - 0xFFE0 8040) 84 10.12 Dynamic Memory Write Recovery Time register (EMCDynamictWR - 0xFFE0 8044)10.13 Dynamic Memory Active to Active Command Period register (EMCDynamictRC - 0xFFE0 8048) 85 10.14 Dynamic Memory Auto-refresh Period register (EMCDynamictRFC - 0xFFE0 804C)10.15 Dynamic Memory Exit Self-refresh register (EMCDynamictXSR - 0xFFE0 8050) 86 10.16 Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD - 0xFFE0 8054)10.17 Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD - 0xFFE0 8058) 87 10.18 Static Memory Extended Wait register (EMCStaticExtendedWait - 0xFFE0 8080)10.19 Dynamic Memory Configuration registers (EMCDynamicConfig0-3 - 0xFFE0 8100, 120, 140, 160) 91 10.21 Static Memory Configuration registers (EMCStaticConfig0-3 - 0xFFE0 8200, 220, 240, 260)92 10.22 Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3 - 0xFFE0 8204, 224, 244 ,264)93 10.24 Static Memory Read Delay registers (EMCStaticWaitRd0-3 - 0xFFE0 820C, 22C, 24C, 26C)94 10.26 Static Memory Write Delay registers (EMCStaticWaitwr0-3 - 0xFFE0 8214, 234, 254, 274)10.27 Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3 - 0xFFE0 8218, 238, 258, 278) 95 11. External memory interface100 3. OperationChapter 6: LPC24XX Memory Accelerator Module (MAM) 101 4. Memory Acceleration Module blocksNXP Semiconductors UM10237 4.2 Instruction latches and data latches 4.3 Flash programming Issues 102 5. Memory Accelerator Module operating modes103 6. MAM configuration106 8. MAM usage notes108 2. DescriptionChapter 7: LPC24XX Vectored Interrupt Controller (VIC) 115 4. Interrupt sources119 2. LPC2400 pin packages2.1 LPC2400 180-pin package Chapter 8: LPC24XX Pin configuration2.2 LPC2400 208-pin packages 120 3. LPC2458 pinning information136 4. LPC2460/68 pinning information154 5. LPC2470/78 pinning information174 6. LPC2460/70 boot control176 2. DescriptionChapter 9: LPC24XX Pin connect 177 3. Pin function select register values4. Pin mode select register values 208 7. GPIO usage notes212 5. Ethernet architecture216 6. Pin description240 8. Descriptor and status formats246 9. Ethernet block functional description285 6. LCD controller functional description 286 Fig 36. LCD controller block diagram 6.1 AHB interfaces6.1.1 AMBA AHB slave interface 291 6.4 RAM palette292 293 6.5 Hardware cursor298 6.6 Gray scaler6.7 Upper and lower panel formatters 299 6.8 Panel clock generator6.9 Timing controller 6.10 STN and TFT data select6.10.1 STN displays 6.10.2 TFT displays 6.11 Interrupt generation 300 6.11.1 Master bus error interrupt 6.11.2 Vertical compare interrupt 303 7.1 LCD Configuration register (LCD_CFG, RW - 0xE01F C1B8)7.2 Horizontal Timing register (LCD_TIMH, RW - 0xFFE1 0000)7.2.1 Horizontal timing restrictions 304 305 7.3 Vertical Timing register (LCD_TIMV, RW - 0xFFE1 0004) 306 7.4 Clock and Signal Polarity register (LCD_POL, RW - 0xFFE1 0008)308 7.5 Line End Control register (LCD_LE, RW - 0xFFE1 000C)309 7.6 Upper Panel Frame Base Address register (LCD_UPBASE, RW - 0xFFE1 0010)7.7 Lower Panel Frame Base Address register (LCD_LPBASE, RW - 0xFFE1 0014) 310 7.8 LCD Control register (LCD_CTRL, RW - 0xFFE1 0018)312 7.9 Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C)313 7.10 Raw Interrupt Status register (LCD_INTRAW, RW - 0xFFE1 0020)314 7.11 Masked Interrupt Status register (LCD_INTSTAT, RW - 0xFFE1 0024)7.12 Interrupt Clear register (LCD_INTCLR, RW - 0xFFE1 0028) 315 7.13 Upper Panel Current Address register (LCD_UPCURR, RW - 0xFFE1 002C)7.14 Lower Panel Current Address register (LCD_LPCURR, RW - 0xFFE1 0030) 7.15 Color Palette registers (LCD_PAL, RW - 0xFFE1 0200 to 0xFFE1 03FC) 316 7.16 Cursor Image registers (CRSR_IMG, RW - 0xFFE1 0800 to 0xFFE1 0BFC)317 7.17 Cursor Control register (CRSR_CTRL, RW - 0xFFE1 0C00)7.18 Cursor Configuration register (CRSR_CFG, RW - 0xFFE1 0C04) 318 7.19 Cursor Palette register 0 (CRSR_PAL0, RW - 0xFFE1 0C08)7.20 Cursor Palette register 1 (CRSR_PAL1, RW - 0xFFE1 0C0C) 319 7.21 Cursor XY Position register (CRSR_XY, RW - 0xFFE1 0C10)7.22 Cursor Clip Position register (CRSR_CLIP, RW - 0xFFE1 0C14) 320 7.23 Cursor Interrupt Mask register (CRSR_INTMSK, RW - 0xFFE1 0C20)7.24 Cursor Interrupt Clear register (CRSR_INTCLR, RW - 0xFFE1 0C24) 321 7.25 Cursor Raw Interrupt Status register (CRSR_INTRAW, RW - 0xFFE1 0C28)7.26 Cursor Masked Interrupt Status register (CRSR_INTSTAT, RW - 0xFFE1 0C2C) 322 8. LCD timing diagrams324 9. LCD panel signal usage329 4. Fixed endpoint configuration330 5. Functional descriptionThe architecture of the USB device controller is shown below in Figure 1345. 331 5.1 Analog transceiver5.2 Serial Interface Engine (SIE) 5.3 Endpoint RAM (EP_RAM) 5.4 EP_RAM access control 5.5 DMA engine and bus master interface 5.6 Register interface 5.7 SoftConnect 5.8 GoodLink 332 6. Operational overview333 7. Pin description7.1 USB device usage note 8. Clocking and power management 335 9. Register description347 359 10. Interrupt handling 362 11. Serial interface engine command description363 11.1 Set Address (Command: 0xD0, Data: write 1 byte)11.2 Configure Device (Command: 0xD8, Data: write 1 byte) 364 11.3 Set Mode (Command: 0xF3, Data: write 1 byte)365 11.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes)11.5 Read Test Register (Command: 0xFD, Data: read 2 bytes) 11.6 Set Device Status (Command: 0xFE, Data: write 1 byte) 367 11.9 Read Error Status (Command: 0xFB, Data: read 1 byte)368 11.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))369 11.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1 byte) 11.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte (optional)) 370 11.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))11.14 Validate Buffer (Command: 0xFA, Data: none) 371 12. USB device controller initialization372 13. Slave mode operation13.1 Interrupt generation 13.2 Data transfer for OUT endpoints 13.3 Data transfer for IN endpoints 373 14. DMA operation385 15. Double buffered endpoint operation389 3. Interfaces3.1 Pin descriptionFig 51. USB Host controller block diagram Table 359. USB OTG port pins Pin name Direction Description Pin category VBUS IV via its corresponding PINSEL register, it is driven HIGH internally. USB Connector 3.1.1 USB host usage note 390 3.2 Software interface 393 4. ArchitectureChapter 15: LPC24XX USB OTG controller 394 5. Modes of operation6. Pin configuration 410 8. HNP support418 9. Clocking and power management420 10. USB OTG controller initialization441 5. Architecture444 4. Register description465 5. Architecture467 3. CAN controllersChapter 18: LPC24XX CAN controllers CAN1/2 469 6. CAN controller architecture473 7. Memory map of the CAN blockThe CAN Controllers and Acceptance Filter occupy a number of APB slots, as follows: 8. Register description475 8.1 Mode Register (CAN1MOD - 0xE004 4000, CAN2MOD - 0xE004 8000)476 8.2 Command Register (CAN1CMR - 0xE004 x004, CAN2CMR - 0xE004 8004)478 8.3 Global Status Register (CAN1GSR - 0xE004 x008, CAN2GSR - 0xE004 8008)480 8.4 Interrupt and Capture Register (CAN1ICR - 0xE004 400C, CAN2ICR - 0xE004 800C)484 8.5 Interrupt Enable Register (CAN1IER - 0xE004 4010, CAN2IER - 0xE004 8010)485 8.6 Bus Timing Register (CAN1BTR - 0xE004 4014, CAN2BTR - 0xE004 8014)487 8.7 Error Warning Limit Register (CAN1EWL - 0xE004 4018, CAN2EWL - 0xE004 8018)8.8 Status Register (CAN1SR - 0xE004 401C, CAN2SR - 0xE004 801C) 489 8.9 Receive Frame Status Register (CAN1RFS - 0xE004 4020, CAN2RFS - 0xE004 8020)490 8.10 Receive Identifier Register (CAN1RID - 0xE004 4024, CAN2RID - 0xE004 8024)8.11 Receive Data Register A (CAN1RDA - 0xE004 4028, CAN2RDA - 0xE004 8028) 491 8.12 Receive Data Register B (CAN1RDB - 0xE004 402C, CAN2RDB - 0xE004 802C) 494 9. CAN controller operation9.1 Error handling 9.2 Sleep mode 9.3 Interrupts 9.4 Transmit priority 495 10. Centralized CAN registers497 11. Global acceptance filter12. Acceptance filter modes12.1 Acceptance filter Off mode 12.2 Acceptance filter Bypass mode 12.3 Acceptance filter Operating mode 12.4 FullCAN mode 498 13. Sections of the ID look-up table RAM14. ID look-up table RAM 500 15. Acceptance filter registers506 16. Configuration and search algorithm16.1 Acceptance filter search algorithm 507 17. FullCAN mode518 18. Examples of acceptance filter tables and ID index values526 3. SPI overview4. SPI data transfers 528 5. SPI peripheral details530 6. Pin description534 8. Architecture537 4. Pin descriptions5. Bus description5.1 Texas Instruments synchronous serial frame format 538 5.2 SPI frame format5.2.1 Clock Polarity (CPOL) and Phase (CPHA) control 5.2.2 SPI format with CPOL=0,CPHA=0 539 5.2.3 SPI format with CPOL=0,CPHA=1 540 5.2.4 SPI format with CPOL = 1,CPHA = 0 541 5.2.5 SPI format with CPOL = 1,CPHA = 1 542 5.3 Semiconductor Microwire frame format543 545 6.1 SSPn Control Register 0 (SSP0CR0 - 0xE006 8000, SSP1CR0 - 0xE003 0000)This register controls the basic operation of the SSP controller. 546 6.2 SSPn Control Register 1 (SSP0CR1 - 0xE006 8004, SSP1CR1 - 0xE003 0004)This register controls certain aspects of the operation of the SSP controller. 547 6.3 SSPn Data Register (SSP0DR - 0xE006 8008, SSP1DR - 0xE003 0008)Software can write data to be transmitted to this register, and read data that has been received. 548 6.4 SSPn Status Register (SSP0SR - 0xE006 800C, SSP1SR - 0xE003 000C)6.5 SSPn Clock Prescale Register (SSP0CPSR - 0xE006 8010, SSP1CPSR - 0xE003 0010) 6.6 SSPn Interrupt Mask Set/Clear Register (SSP0IMSC - 0xE006 8014, SSP1IMSC - 0xE003 0014) 549 6.7 SSPn Raw Interrupt Status Register (SSP0RIS - 0xE006 8018, SSP1RIS - 0xE003 0018)6.8 SSPn Masked Interrupt Status Register (SSP0MIS - 0xE006 801C, SSP1MIS - 0xE003 001C) 550 6.9 SSPn Interrupt Clear Register (SSP0ICR - 0xE006 8020, SSP1ICR - 0xE003 0020)6.10 SSPn DMA Control Register (SSP0DMACR - 0xE006 8024, SSP1DMACR - 0xE003 0024) 551 3. Features of the MCI4. SD/MMC card interface pin descriptionChapter 21: LPC24XX SD/MMC card interface 552 5. Functional overview574 6. I2C operating modes577 7. I2C implementation and operation581 8. Register description582 8.1 I2C Control Set Register (I2C[0/1/2]CONSET: 0xE001C000, 0xE005 C000, 0xE008 0000)584 8.2 I2C Control Clear Register (I2C[0/1/2]CONCLR: 0xE001 C018, 0xE005 C018, 0xE008 0018)8.3 I2C Status Register (I2C[0/1/2]STAT - 0xE001 C004, 0xE005 C004, 0xE008 0004) 585 8.4 I2C Data Register (I2C[0/1/2]DAT - 0xE001 C008, 0xE005 C008, 0xE008 0008)8.5 I2C Slave Address Register (I2C[0/1/2]ADR - 0xE001 C00C, 0xE005 C00C, 0xE008 000C) 8.6 I2C SCL High Duty Cycle Register (I2C[0/1/2]SCLH - 0xE001 C010, 0xE005 C010, 0xE008 0010) 8.7 I2C SCL Low Duty Cycle Register (I2C[0/1/2]SCLL - 0xE001 C014, 0xE005 C014, 0xE008 0014) 8.8 Selecting the appropriate I2C data rate and duty cycle 586 9. Details of I2C operating modes603 10. Software example612 4. Pin descriptions617 6. I2S transmit and receive interfaces618 7. FIFO controller619 System signaling occurs when a level detection is true and enabled. 621 Chapter 24: LPC24XX Timer0/1/2/3622 5.1 Multiple CAP and MAT pins 624 6.1 Interrupt Register (T[0/1/2/3]IR - 0xE000 4000, 0xE000 8000, 0xE007 0000, 0xE007 4000)The Timer Control Register (TCR) is used to control the operation of the Timer/Counter. 6.2 Timer Control Register (T[0/1/2/3]CR - 0xE000 4004, 0xE000 8004, 0xE007 0004, 0xE007 4004) 625 6.3 Count Control Register (T[0/1/2/3]CTCR - 0xE000 4070, 0xE000 8070, 0xE007 0070, 0xE007 4070)626 6.4 Timer Counter registers (T0TC - T3TC, 0xE000 4008, 0xE000 8008, 0xE007 0008, 0xE007 4008)6.5 Prescale register (T0PR - T3PR, 0xE000 400C, 0xE000 800C, 0xE007 000C, 0xE007 400C) 6.6 Prescale Counter register (T0PC - T3PC, 0xE000 4010, 0xE000 8010, 0xE007 0010, 0xE007 4010) 6.7 Match Registers (MR0 - MR3) 627 6.8 Match Control Register (T[0/1/2/3]MCR - 0xE000 4014, 0xE000 8014, 0xE007 0014, 0xE007 4014)628 6.9 Capture Registers (CR0 - CR3)6.10 Capture Control Register (T[0/1/2/3]CCR - 0xE000 4028, 0xE000 8028, 0xE007 0028, 0xE007 4028) 629 6.11 External Match Register (T[0/1/2/3]EMR - 0xE000 403C, 0xE000 803C, 0xE007 003C, 0xE007 403C)630 7. Example timer operation8. Architecture 637 5. PWM base addresses648 4. Architecture656 7. Alarm register group8. Alarm output 9. RTC usage notes 657 10. RTC clock generation660 11. Battery RAM12. RTC external 32 kHz oscillator component selection 663 4. Register description666 5. Block diagram673 6. Operation6.1 Hardware-triggered conversion 6.2 Interrupts 6.3 Accuracy vs. digital receiver 674 4. Register description (DACR - 0xE006 C000)Chapter 29: LPC24XX Digital-to Analog Converter (DAC) 675 5. Operation676 2. Flash boot loader5. DescriptionChapter 30: LPC24XX Flash memory programming firmware 680 6. Boot process flowchartFig 139. Boot process flowchart 681 7. Sector numbers682 8. Code Read Protection (CRP)683 9. ISP commands690 10. IAP commands696 11. JTAG Flash programming interface700 5. Boot process flowchart(1) For details on handling the crystal frequency, see Section 317.4 Reinvoke ISP on page 709 Fig 142. Boot process flowchart 701 6. ISP commands706 7. IAP commands711 3. Features of the GPDMAChapter 32: LPC24XX General Purpose DMA (GPDMA) controller 712 4. Functional overview713 4.2.1 AHB Slave Interface 4.2.2 Control Logic and Register Bank 4.2.3 DMA Request and Response Interface 4.2.4 Channel Logic and Channel Register Bank 4.2.5 Interrupt Request 4.2.6 AHB Master Interface 714 4.2.7 Bus and transfer widths 4.2.8 Endian behavior 716 4.2.9 Error conditions4.2.10 Channel hardware 4.2.11 DMA request priority 4.2.12 Interrupt generation 4.2.13 The completion of the DMA transfer indication 717 4.3 DMA system connections718 5. Programming the GPDMA733 7. Address generation8. Scatter/Gather 735 9. Interrupt requests9.1 Hardware interrupt sequence flow 9.2 Interrupt polling sequence flow 736 10. GPDMA data flow739 11. Fl ow contr ol742 5. JTAG function select7. Block diagram 746 6. Reset state of multiplexed pins747 7. Block diagram751 4. How to enable RealMonitor756 5. RealMonitor build options759 1. AbbreviationsChapter 36: LPC24XX Supplementary information 760 2. Legal information2.1 Definitions 2.2 Disclaimers 2.3 Trademarks 761 3. Tables773 4. Figures775 5. Contents
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