NXP Semiconductors UM10237 , 5.1 Multiple CAP and MAT pins

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 622 o f 792
NXP Semiconductors UM10237
Chapter 24: LPC24XX Timer0/1/2/3
•Free running timer.
4. Description
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally-supplied clock, and can optionally generate interrupts or perform other actions
at specified timer values, based on four match registers. It also includes four capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
5. Pin description
Table24–545 gives a brief summary of each of the Timer/Counter related pins.
5.1 Multiple CAP and MAT pins
Software can select multiple pins for most of the CAP or MAT functions in the Pin Select
registers, which are described in Section 9–3. When more than one pin is selected for a
MAT output, all such pins are driven identically. When more than one pin is selected for a
CAP input, the pin with the lowest port number is used.
6. Register description
Each Timer/Counter contains the registers shown in Table 24–546 ("Reset Value" refers to
the data stored in used bits only; it does not include reserved bits content). More detailed
descriptions follow.
Table 545. Timer/Counter pin description
Pin Type Description
CAP0[1:0]
CAP1[1:0]
CAP2[1:0]
CAP3[1:0]
Input Capture Signals- A transition on a capture pin can be configured to load on e
of the Capture Registers with the value in the Timer Counter and optionally
generate an interrupt. Capture functionality can be selected from a number
of pins. When more than one pin is selected for a Capture input on a single
TIMER0/1 channel, the pin with the lowest Port number is used
Timer/Counter block can select a capture signal as a clock source instead of
the PCLK derived clock. For more details see Section 24–6.3 “Count Control
Register (T[0/1/2/3]CTCR - 0xE000 4070, 0xE000 8070, 0xE007 0070,
0xE007 4070)” on page 625.
MAT0[1:0]
MAT1[2:0]
MAT2[3:0]
MAT3[3:0]
Output External Match Output 0/1- When a match register 0/1 (MR3:0) equals the
timer counter (TC) this output can either toggle, go low, go high, or do
nothing. The External Match Register (EMR) controls the functionality of this
output. Match Output functionality can be selected on a number of pins in
parallel.