NXP Semiconductors UM10237 5.3.16 APB interfaces, 5.3.17 Interrupt logic

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 563 o f 792
NXP Semiconductors UM10237
Chapter 21: LPC24XX SD/MMC card interface
5.3.16 APB interfaces
The APB interface generates the interrupt and DMA requests, and accesses the MCI
adapter registers and the data FIFO. It consists of a data path, register decoder, and
interrupt/DMA logic. DMA is controlled by the General Purpose DMA controller, see that
chapter for details.
5.3.17 Interrupt logic
The interrupt logic generates an interrupt request signal that is asserted when at least one
of the selected status flags is HIGH. A mask register is provided to allow selection of the
conditions that will generate an interrupt. A status flag generates the interrupt request if a
corresponding mask flag is set.
6. Register description
The MCI registers are shown in Table21–490.
Table 489. Rec eive FI FO status flags
Symbol Description
RxFifoFull Set to HIGH when all 16 receive FIFO words contain valid data.
RxFifoEmpty Set to HIGH when the receive FIFO does not contain valid data.
RxHalfFull Set to HIGH when 8 or more receive FIFO words contain valid data. This
flag can be used as a DMA request.
RxDataAvlbl Set to HIGH when the receive FIFO is not empty. This flag is the inverse
of the RxFifoEmpty flag.
RxOverrun Set to HIGH when an overrun error occurs. This flag is cleared by writing
to the MCIClear register.
Table 490. Summary of MCI registers
Name Description Access Width Reset
Value [1] Address
MCIPower Power control register. R/W 8 0x00 0xE008 C000
MCIClock Clock control register. R/W 12 0x000 0xE008 C004
MCIArgument Argument register. R/W 32 0x00000000 0xE008 C008
MMCCommand Command register. R/W 11 0x000 0xE008 C00C
MCIRespCmd Response command register. RO 6 0x00 0xE008 C010
MCIResponse0 Response register. RO 32 0x00000000 0xE008 C014
MCIResponse1 Response register. RO 32 0x00000000 0xE008 C018
MCIResponse2 Response register. RO 32 0x00000000 0xE008 C01C
MCIResponse3 Response register. RO 31 0x00000000 0xE008 C020
MCIDataTimer Data Timer. R/W 32 0x00000000 0xE008 C024
MCIDataLength Data control register. R/W 16 0x0000 0xE008 C028
MCIDataCtrl Data control register. R/W 8 0x00 0xE008 C02C
MCIDataCnt Data counter. RO 16 0x0000 0xE008 C030
MCIStatus Status register. RO 22 0x000000 0xE008 C034
MCIClear Clear register. WO 11 - 0 xE008C038