NXP Semiconductors UM10237 8.5 Interrupt Enable Register (CAN1IER - 0xE004 4010, CAN2IER - 0xE004 8010)

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 484 o f 792
NXP Semiconductors UM10237
Chapter 18: LPC24XX CAN controllers CAN1/2
[1] The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command
“Release Receive Buffer” will clear RI temporarily. If there is another message available within the Receive
Buffer after the release command, RI is set again. Otherwise RI remains cleared.
[2] A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is
involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the
according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.
[3] Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time,
the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The
content within this register is fixed until the user software has read out its content once. From now on, the
capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt.
[4] On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current
bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content
within this register is fixed until the user application has read out its contents once. From now on, the
capture mechanism is activated again.
8.5 Interrupt Enable Register (CAN1IER - 0xE004 4010, CAN2IER -
0xE004 8010)
This read/write register controls whether various events on the CAN controller will result in
an interrupt or not. Bits 10:0 in this register correspond 1-to-1 with bits 10:0 in the
CANxICR register. If a bit in the CANxIER register is 0 the corresponding interrupt is
disabled; if a bit in the CANxIER register is 1 the corresponding source is enabled to
trigger an interrupt.
31:24 ALCBIT[4] - Each time arbitration is lost while trying to send on the
CAN, the bit number within the frame is captured into
this field. After the content of ALCBIT is read, the ALI
bit is cleared and a new Arbitration Lost interrupt can
occur.
0X
00 arbitration lost in the first bit (MS) of identifier
... a
11 arbitration lost in SRTS bit (RTR bit for standard frame
messages)
12 arbitration lost in IDE bit
13 arbitration lost in 12th bit of identifier (extended frame
only)
...
30 arbitration lost in last bit of identifier (extended frame
only)
31 arbitration lost in RTR bit (extended frame only)
Table 423. Interr upt and Capture Register (CAN1ICR - address 0xE0 04400C, CAN2IC R -
address 0xE004 800C) bit description
Bit Symbol Value Function Reset
Value RM Set