UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 90 of 792
NXP Semiconductors UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
A chip select can be connected to a single memory device, in this case the chip select
data bus width is the same as the device width. Alternatively the chip select can be
connected to a number of external devices. In this case the chip select data bus width is
the sum of the memory device data bus widths.
For example, for a chip select connected to:
•A 32 bit wide memory device, choose a 32 bit wide address mapping.
•A 16 bit wide memory device, choose a 16 bit wide address mapping.
•Four x 8 bit wide memory devices, choose a 32 bit wide address mapping.
•Two x 8 bit wide memory devices, choose a 16 bit wide address mapping.
10.20 Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3 - 0xFFE0 8104, 124, 144, 164)
The EMCDynamicRasCas0-3 registers enable you to program the RAS and CAS
latencies for the relevant dynamic memory. It is recommended that these registers are
modified during system initialization, or when there are no current or outstanding
transactions. This can be ensured by waiting until the EMC is idle, and then entering
low-power, or disabled mode. These registers are accessed with one wait state.
Note: The values programmed into these registers must be consistent with the values
used to initialize the SDRAM memory device.
Table5–88 shows the bit assignments for the EMCDynamicRasCas0-3 registers.
1 1 011 10 256 MB (8Mx32), 4 banks, row length = 13, column length = 8
1 1 100 00 512 MB (64Mx8), 4 banks, row length = 13, column length = 11
1 1 100 01 512 MB (32Mx16), 4 banks, row length = 13, column length = 10
Table 87. Address mapping
14 12 11:9 8:7 Description
Table 88. Dynamic Memory RAS & CAS Delay registers (EMCDynamicRasCas0-3 - address
0xFFE0 8104, 0xFFE0 8124, 0xFFE0 8144, 0xFFE0 8164) bit description
Bit Symbol Value Description Reset
Value
1:0 RAS latency
(active to
read/write
delay) (RAS)
00 Reserved. 11
01 One CCLK cycle.
10 Two CCLK cycles.
11 Three CCLK cycles (POR reset value).
7:2 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
9:8 CAS latency
(CAS) 00 Reserved. 11
01 One CCLK cycle.
10 Two CCLK cycles.
11 Three CCLK cycles (POR reset value).
31:10 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA