UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 651 o f 792
NXP Semiconductors UM10237
Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
6.2.2 Clock Tick Counter Register (CTCR - 0xE002 4004)
The Clock Tick Counter is read only. It can be reset to zero through the Clock Control
Register (CCR). The CTC consists of the bits of the clock divider counter.
If the RTC is driven by the external 32.786 kHz oscillator, subsequent read operations of
the CTCR may yield an incorrect result. The CTCR is implemented as a 15-bit ripple
counter so that not all 15 bits change simultaneously. The LSB changes first, then the
next, and so forth. Since the 32.786 kHz oscillator is asynchronous to the CPU clock, it is
possible for a CTC read to occur during the time when the CTCR bits are changing
resulting in an incorrect large difference between back-to-back reads.
If the RTC is driven by the PCLK, the CPU and the RTC are synchronous because both of
their clocks are driven from the PLL output. Therefore, incorrect consecutive reads can
not occur.
6.2.3 Clock Control Register (CCR - 0xE002 4008)
The clock register is a 4 bit register that controls the operation of the clock divide circuit.
Each bit of the clock register is described in Table26–570.
Table 568. Interrupt Location Register (ILR - address 0xE002 4000) bit description
Bit Symbol Description Reset
value
0 RTCCIF When one, the Counter Increment Interrupt block generated an interrupt.
Writing a one to this bit location clears the counter increment interrupt. NC
1 RTCALF When one, the alarm registers generated an interrupt. Writing a one to
this bit location clears the alarm interrupt. NC
2 RTSSF When one, the Counter Increment Sub-Seconds interrupt is generated.
The interrupt rate is determined by the CISS register. NC
7:2 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
Table 569. Clock Tick Counter Register (CTC R - address 0xE00240 04) bit des cription
Bit Symbol Description Reset
value
0 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
15:1 Clock Tick
Counter Prior to the Seconds counter, the CTC counts 32,768 clocks per
second. Due to the RTC Prescaler, these 32,768 time increments may
not all be of the same duration. Refer to the Section 26–10.1
“Reference Clock Divider (Prescaler)” on page 657 for details.
NA
Table 570. Clock Con t rol Reg ister (CCR - address 0xE002 4008) bit description
Bit Symbol Description Reset
value
0 CLKEN Clock Enable. When this bit is a one the time counters are enabled.
When it is a zero, they are disabled so that they may be initialized. NA
1 CTCRST CTC Reset. When one, the elements in the Clock Tick Counter are
reset. The elements remain reset until CCR[1] is changed to zero. NA