NXP Semiconductors UM10237 3.2.2 PLL and startup/boot code interaction, 3.2.3 PLL register description

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 47 of 792
NXP Semiconductors UM10237
Chapter 4: LPC24XX Clocking and power control
PLL activation is controlled via the PLLCON register. The PLL multiplier and divider
values are controlled by the PLLCFG register. These two registers are protected in order
to prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all
chip operations, including the Watchdog Timer, could be dependent on the PLL if so
configured (for example when it is providing the chip clock), accidental changes to the PLL
setup could result in unexpected or fatal behavior of the microcontroller. The protection is
accomplished by a feed sequence similar to that of the Watchdog Timer. Details are
provided in the description of the PLLFEED register.
The PLL is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL is enabled by software only.
It is important that the setup procedure described in Section 4–3.2.14 “PLL setup
sequence” is followed as is or the PLL might not operate at all!.
3.2.2 PLL and startup/boot code interaction
The boot code for the LPC2400 is a different from previous NXP ARM7 LPC2000 chips.
When there is no valid code (determined by the checksum word) in the user flash or the
ISP enable pin (P2.10) is pulled low on startup, the ISP mode will be entered and the boot
code will setup the PLL with the IRC. Therefore it can not be assumed that the PLL is
disabled when the user opens a debug session to debug the application code. The user
startup code must follow the steps described in this chapter to disconnect the PLL.
The boot code may also change the values for some registers when the chip enters ISP
mode. For example, the GPIOM bit in the SCS register is set in the ISP mode. If the user
doesn't notice it and clears the GPIOM bit in the application code, the application code will
not be able to operate with the traditional GPIO function on PORT0 and PORT1.
3.2.3 PLL register description
The PLL is controlled by the registers shown in Tabl e 4–4 3. More detailed descriptions
follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic
zero.
Warning: Improper setting of PLL values may result in incorrect operation of the
device!
Fig 14. PLL block diagram (N = 16, M = 125, USBSEL = 6, CCLKSEL = 4)
N-DIVIDER
M-DIVIDER
PHASE-
FREQUENCY
DETECTOR
FILTER CCO
/2
CPU
CLOCK
DIVIDER
cclk =
72 MHz
CCLKSEL[7:0]
PLOCK
PLLE
PLLC
pd
USB
CLOCK
DIVIDER usbclk =
48 MHz
USBSEL[3:0]
refclk =
1.152 MHz
pllclkin =
18.432 MHz
pllclk =
288 MHz
/16
/125
1.152 MHz 144 MHz 288 MHz
288
MHz
/6
/4
NSEL[23:16]
MSEL[14:0]