NXP Semiconductors UM10237 - page 205

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 205 o f 792
NXP Semiconductors UM10237
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
Aside from the 32-bit long and word only accessible FIOMASK register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table10–174, too. Next to providing the same functions as the FIOMASK register, these
additional registers allow easier and faster access to the physical port pins.
Table 173. Fast GPIO po rt Ma sk register (FIO[0/1/2/3/4]MASK - address
0x3FFF C0[1/3/5/7/9]0) bit description
Bit Symbol Value Description Reset
value
31:0 FP0xMASK,
FP1xMASK,
FP2xMASK,
FP3xMASK
FP4xMASK
Fast GPIO physical pin access control. 0x0
0 Controlled pin is affected by writes to the port’s FIOSET,
FIOCLR, and FIOPIN register(s). Current state of the pin can
be read from the FIOPIN register.
1 Controlled pin is not affected by writes into the port’s
FIOSET, FIOCLR and FIOPIN register(s). When the FIOPIN
register is read, this bit will not be updated with the state of
the physical pin.
Table 174. Fast GPIO po rt Mask byte and half-word accessible register description
Generic
Register
name
Description Register
length (bits)
& access
Reset
value PORTn Register Address & Name
FIOxMASK0 Fast GPIO Port x Mask
register 0. Bit 0 in
FIOxMASK0 register
corresponds to pin Px.0 ...
bit 7 to pin Px.7.
8 (byte)
R/W 0x0 FIO0MASK0 - 0x3FFF C010 FIO1MASK0 - 0x3FFF C030
FIO2MASK0 - 0x3FFF C050
FIO3MASK0 - 0x3FFF C070
FIO4MASK0 - 0x3FFF C090
FIOxMASK1 Fast GPIO Port x Mask
register 1. Bit 0 in
FIOxMASK1 register
corresponds to pin Px.8 ...
bit 7 to pin Px.15.
8 (byte)
R/W 0x0 FIO0MASK1 - 0x3FFF C011 FIO1MASK1 - 0x3FFF C031
FIO2MASK1 - 0x3FFF C051
FIO3MASK1 - 0x3FFF C071
FIO4MASK1 - 0x3FFF C091
FIOxMASK2 Fast GPIO Port x Mask
register 2. Bit 0 in
FIOxMASK2 register
corresponds to pin Px.16 ...
bit 7 to pin Px.23.
8 (byte)
R/W 0x0 FIO0MASK2 - 0x3FFF C012 FIO1MASK2 - 0x3FFF C032
FIO2MASK2 - 0x3FFF C052
FIO3MASK2 - 0x3FFF C072
FIO4MASK2 - 0x3FFF C092
FIOxMASK3 Fast GPIO Port x Mask
register 3. Bit 0 in
FIOxMASK3 register
corresponds to pin Px.24 ...
bit 7 to pin Px.31.
8 (byte)
R/W 0x0 FIO0MASK3 - 0x3FFF C013 FIO1MASK3 - 0x3FFF C033
FIO2MASK3 - 0x3FFF C053
FIO3MASK3 - 0x3FFF C073
FIO4MASK3 - 0x3FFF C093
FIOxMASKL Fast GPIO Port x Mask
Lower half-word register.
Bit 0 in FIOxMASKL
register corresponds to pin
Px.0 ... bit 15 to pin Px.15.
16
(half-word)
R/W
0x0 FIO0MASKL - 0x3FFF C010
FIO1MASKL - 0x3FFF C030
FIO2MASKL - 0x3FFF C050
FIO3MASKL - 0x3FFF C070
FIO4MASKL - 0x3FFF C090
FIOxMASKU Fast GPIO Port x Mask
Upper half-word register.
Bit 0 in FIOxMASKU
register corresponds to pin
Px.16 ... bit 15 to Px.31.
16
(half-word)
R/W
0x0 FIO0MASKU - 0x3FFF C012
FIO1MASKU - 0x3FFF C032
FIO2MASKU - 0x3FFF C053
FIO3MASKU - 0x3FFF C072
FIO4MASKU - 0x3FFF C092