UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 561 o f 792
NXP Semiconductors UM10237
Chapter 21: LPC24XX SD/MMC card interface

5.3.11 Status flags

Table21–487 lists the data path status flags (see Section 21–6.11 “Status Register
(MCIStatus - 0xE008 C034)” on page 569 for more information).

5.3.12 CRC generator

The CRC generator calculates the CRC checksum only for the data bits in a single block,
and is bypassed in data stream mode. The checksum is a 16bit value:
CRC[15:0] = Remainder [(M(x) × x15) / G(x)]
G(x) = x16 + x12 + x5 + 1
M(x) - (first data bit) × xn + ... + (last data bit) ¥ X0

5.3.13 Data FIFO

The data FIFO (first-in-first-out) subunit is a data buffer with transmit and receive logic.
The FIFO contains a 32 bit wide, 16-word deep data buffer, and transmit and receive
logic. Because the data FIFO operates in the APB clock domain (PCLK), all signals from
the subunits in the MCI clock domain (MCLK) are resynchronized.
Depending on TxActive and RxActive, the FIFO can be disabled, transmit enabled, or
receive enabled. TxActive and RxActive are driven by the data path subunit and are
mutually exclusive:
•The transmit FIFO refers to the transmit logic and data buffer when TxActive is
asserted (see Section 21–5.3.14 “Transmit FIFO”)
Table 487. Data path status flags
Flag Description
TxFifoFull Transmit FIFO is full.
TxFifoEmpty Transmit FIFO is empty.
TxFifoHalfEmpty Transmit FIFO is half full.
TxDataAvlbl Transmit FIFO data available.
TxUnderrun Transmit FIFO underrun error.
RxFifoFull Receive FIFO is full.
RxFifoEmpty Receive FIFO is empty.
RxFifoHalfFull Receive FIFO is half full.
RxDataAvlbl Receive FIFO data available.
RxOverrun Receive FIFO overrun error.
DataBlockEnd Data block sent/received.
StartBitErr Start bit not detected on all data signals in wide bus mode.
DataCrcFail Data packet CRC failed.
DataEnd Data end (data counter is zero).
DataTimeOut Data timeout.
TxActive Data transmission in progress.
RxActive Data reception in progress.