NXP Semiconductors UM10237 - page 451

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 451 o f 792
NXP Semiconductors UM10237
Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
[1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
[2] For details see Section 17–4.10 “UART1 Line Status Register (U1LSR - 0xE0010014, Read Only)”
[3] For details see Section 17–4.1 “UART1 Receiver Buffer Register (U1RBR - 0xE0010000, when DLAB = 0
Read Only)”
[4] For details see Section 17–4.5 “UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read Only)”
and Section 17–4.2 “UART1 Transmitter Holding Register (U1THR - 0xE0010000 when DLAB = 0, Write
Only)”
The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated
when the UART1 THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART1 THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U1THR at one time since
the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U1THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART1 THR FIFO has held two or more characters at one time and
currently, the U1THR is empty . The THRE interrupt is reset when a U1THR write occurs or
a read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001).
Table 403: UART1 Interrupt Handling
U1IIR[3:0]
value[1] Priority Interrupt Type Interrupt Source Interrupt Reset
0001 - None None -
0110 Highest RX Line
Status /
Error
OE[2] or PE[2] or FE[2] or BI[2] U1LSR
Read[2]
0100 Second RX Data
Available Rx data available or trigger level reached in FIFO (U1FCR0=1) U1RBR Read[3] or
UART1
FIFO drops
below
trigger level
1100 Second Character
Time-ou t
indication
Minimum of one character in the RX FIFO and no
character input or removed during a time period
depending on how many characters are in FIFO
and what the trigger level is set at (3.5 to 4.5
character times).
The exact time will be:
[(word length) × 7 - 2] × 8 + [(trigger level - number
of characters) × 8 + 1] RCLKs
U1RBR
Read[3]
0010 Third THRE THRE[2] U1IIR
Read[4] (if
source of
interrupt) or
THR write
0000 Fourth Modem
Status CTS or DSR or RI or DCD MSR Read