UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 55 of 792
NXP Semiconductors UM10237
Chapter 4: LPC24XX Clocking and power control
M = (FCCO × N) / (2 × FIN)
Start by assuming N = 1, since this produces the smallest multiplier needed for the PLL.
So, M = 288 ×106/(2×4×106) = 36. Since the result is an integer, there is no need to
look further for a good set of PLL configuration values. The value written to PLLCFG
would be 0x23 (N - 1 = 0; M - 1 = 35 = 0x23).
The potential CPU clock rate can be determined by dividing FCCO by the desired CPU
frequency: 288 ×106/60×106= 4.8. The nearest integer value for the CPU Clock
Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
If it is important to obtain exactly 60 MHz, an FCCO rate must be found that can be divided
down to both 48 MHz and 60 MHz. The only possibility is 480 MHz. Divided by 10, this
gives the 48 MHz with a 50% duty cycle needed by the USB block. Divided by 8, it gives
60 MHz for the CPU clock. PLL settings for 480 MHz are N = 1 and M = 60.
Example 2)
Assumptions:
•The USB interface will not be used in the application.
•The desired CPU rate = 72 MHz
•The 32.768 kHz RTC clock source will be used as the system clock source
Calculations:
M = (FCCO × N) / (2 × FIN)
The smallest frequency for FCCO that can produce our desired CPU clock rate and is
within the PLL operating range is 288 MHz (4 ×72 MHz). Start by assuming N = 1, since
this produces the smallest multiplier needed for the PLL.
So, M = 288 ×106/(2×32,768) = 4,394.53125. This is not an integer, so the CPU
frequency will not be exactly 288 MHz with this setting. Since this case is less obvious, it
may be useful to make a table of possibilities for different values of N (see Table4–52).
Beyond N = 7, the value of M is out of range or not supported, so the table stops there. In
the table, the calculated M value is rounded to the nearest integer. If this results in CCLK
being above the maximum operating frequency (72 MHz), it is allowed if it is not more th an
1/2 % above the maximum frequency.
Table 52. Potential values for PLL example
N M M Rounded FREF (Hz) FCCO (MHz) Actual
CCLK (MHz) % Error
1 4394.53125 4395 32768 288.0307 72.0077 0.0107
2 8789.0625 8789 16384 287.9980 71.9995 -0.0007
3 13183.59375 13184 10922.67 288.0089 72.0022 0.0031
4 17578.125 17578 8192 287.9980 71.9995 -0.00 07
5 21972.65625 21973 6553.6 288.0045 72.0011 0.0016