NXP Semiconductors UM10237 user manual ,

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 54 of 792
NXP Semiconductors UM10237
Chapter 4: LPC24XX Clocking and power control
3.2.12 Procedure for determining PLL settings
PLL parameter determination can be simplified by using a spreadsheet available from
NXP. To determine PLL parameters by hand, the following general procedure may be
used:
1. Determine if the application requires use of the USB interface. The USB requires a
50% duty cycle clock of 48 MHz within a very small tolerance, which means that FCCO
must be an even integer multiple of 48 MHz (i.e. an integer multiple of 96 MHz), within
a very small tolerance.
2. Choose the desired processor operating frequency (cclk). This may be based on
processor throughput requirements, need to support a specific set of UART baud
rates, etc. Bear in mind that peripheral devices may be running from a lower clock
frequency than that of the processor (see Section 4–3.3 “Clock dividers” on page 56
and Section 4–3.4 “Power control” on page 59). Find a value for FCCO that is close to
a multiple of the desired cclk frequency, bearing in mind the requirement for USB
support in [1] above, and that lower values of FCCO result in lower power dissipation.
3. Choose a value for the PLL input frequency (FIN). This can be a clock obtained from
the main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support,
the main oscillator should be used.
4. Calculate values for M and N to produce a sufficiently accurate FCCO frequency. The
desired M value -1 will be written to the MSEL field in PLLCFG. The desired N value -1
will be written to the NSEL field in PLLCFG.
In general, it is better to use a smaller value for N, to reduce the level of multiplication that
must be accomplished by the CCO. Due to the difficulty in finding the best values in some
cases, it is recommended to use a spreadsheet or similar method to show many
possibilities at once, from which an overall best choice may be selected. A spreadsheet is
available from NXP for this purpose.
3.2.13 Examples of PLL settings
The following examples illustrate selecting PLL values based on different system
requirements.
Example 1)
Assumptions:
•The USB interface will be used in the application. The lowest integer multiple of
96 MHz that falls within the PLL operating range (288 MHz) will be targeted.
•The desired CPU rate = 60 MHz.
•An external 4 MHz crystal or clock source will be used as the system clock source.
Calculations:
16479 17578 18127 18311 19226
19775 20508 20599 20874 21149
21973 23071 23438 23804 24170
Table 51. Additional Multiplier Values for use with a Low Frequency Clock Input
Low Frequency PLL Multipliers