NXP Semiconductors UM10237

User manual Rev. 02 — 19 December 2008 764 o f 792

Chapter 36: LPC24XX Supplementary information

Table 175.GPIO overall Interrupt Status register (IOIntStatus

- address 0xE002 8080) bit description . . . . .206

Table 176.GPIO Interrupt Enable for Rising edge register

(IO0IntEnR - address 0xE002 8090 and

IO2IntEnR - address 0xE002 80B0)

bit description. . . . . . . . . . . . . . . . . . . . . . . . .206

Table 177.GPIO Interrupt Enable for Falling edge register

(IO0IntEnF - address 0xE002 8094 and

IO2IntEnF - address 0xE002 80B4)

bit description. . . . . . . . . . . . . . . . . . . . . . . . .206

Table 178.GPIO Status for Rising edge register (IO0IntStatR

- address 0xE002 8084 and IO2IntStatR - address

0xE002 80A4) bit description . . . . . . . . . . . . .207

Table 179.GPIO Status for Falling edge register (IO0IntStatF

- address 0xE002 8088 and IO2IntStatF - address

0xE002 80A8) bit description . . . . . . . . . . . . .207

Table 180.GPIO Status for Falling edge register (IO0IntClr -

address 0xE002 808C and IO2IntClr - address

0xE002 80AC) bit description. . . . . . . . . . . . .207

Table 181.Ethernet acronyms, abbreviations,

and definitions . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 182.Example PHY Devices. . . . . . . . . . . . . . . . . .214

Table 183.Ethernet MII pin descriptions . . . . . . . . . . . . .216

Table 184.Ethernet RMII pin descriptions. . . . . . . . . . . .217

Table 185.Ethernet MIIM pin descriptions. . . . . . . . . . . . 217

Table 186.Summary of Ethernet registers. . . . . . . . . . . .218

Table 187.MAC Configuration register 1 (MAC1 - address

0xFFE0 0000) bit description . . . . . . . . . . . . .220

Table 188.MAC Configuration register 2 (MAC2 - address

0xFFE0 0004) bit description . . . . . . . . . . . . .220

Table 189. Pad operation . . . . . . . . . . . . . . . . . . . . . . . .221

Table 190.Back-to-back Inter-packet-gap register (IPGT -

address 0xFFE0 0008) bit description . . . . . .222

Table 191. Non Back-to-back Inter-packet-gap register

(IPGR - address 0xFFE0 000C) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .222

Table 192.Collision Window / Retry register (CLRT - address

0xFFE0 0010) bit description . . . . . . . . . . . . .223

Table 193.Maximum Frame register (MAXF - address

0xFFE0 0014) bit description . . . . . . . . . . . . .223

Table 194.PHY Support register (SUPP - address

0xFFE0 0018) bit description . . . . . . . . . . . . .223

Table 195. Test register (TEST - address 0xFFE0) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .224

Table 196.MII Mgmt Configuration register (MCFG - address

0xFFE0 0020) bit description . . . . . . . . . . . . .224

Table 197. Clock select encoding . . . . . . . . . . . . . . . . . .224

Table 198.MII Mgmt Command register (MCMD - address

0xFFE0 0024) bit description . . . . . . . . . . . . .225

Table 199.MII Mgmt Address register (MADR - address

0xFFE0 0028) bit description . . . . . . . . . . . . .225

Table 200.MII Mgmt Write Data register (MWTD - address

0xFFE0 002C) bit description. . . . . . . . . . . . .225

Table 201.MII Mgmt Read Data register (MRDD - address

0xFFE0 0030) bit description . . . . . . . . . . . . .225

Table 202.MII Mgmt Indicators register (MIND - address

0xFFE0 0034) bit description . . . . . . . . . . . . .226

Table 203.Station Address register (SA0 - address

0xFFE0 0040) bit description. . . . . . . . . . . . . 226

Table 204.Station Address register (SA1 - address

0xFFE0 0044) bit description. . . . . . . . . . . . . 227

Table 205.Station Address register (SA2 - address

0xFFE0 0048) bit description. . . . . . . . . . . . . 227

Table 206.Command register (Command - address

0xFFE0 0100) bit description. . . . . . . . . . . . . 227

Table 207.Status register (Status - address 0xFFE0 0104) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .228

Table 208.Receive Descriptor Base Address register

(RxDescriptor - address 0xFFE0 0108) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .228

Table 209.receive Status Base Address register (RxStatus -

address 0xFFE0 010C) bit description. . . . . . 229

Table 210.Receive Number of Descriptors register

(RxDescriptor - address 0xFFE0 0110) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .229

Table 211.Receive Produce Index register (RxProduceIndex

- address 0xFFE0 0114) bit description. . . . . 229

Table 212.Receive Consume Index register

(RXConsumeIndex - address 0xFFE0 0118) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .230

Table 213.Transmit Descriptor Base Address register

(TxDescriptor - address 0xFFE0 011C) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .230

Table 214.Transmit Status Base Address register (TxStatus -

address 0xFFE0 0120) bit description. . . . . . 231

Table 215.Transmit Number of Descriptors register

(TxDescriptorNumber - address 0xFFE0 0124) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .231

Table 216.Transmit Produce Index register (TxProduceIndex

- address 0xFFE0 0128) bit description. . . . . 231

Table 217.Transmit Consume Index register

(TxConsumeIndex - address 0xFFE0 012C) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .232

Table 218. Transmit Status Vector 0 register (TSV0 - address

0xFFE0 0158) bit description. . . . . . . . . . . . . 232

Table 219.Transmit Status Vector 1 register (TSV1 - address

0xFFE0 015C) bit description . . . . . . . . . . . . 233

Table 220.Receive Status Vector register (RSV - address

0xFFE0 0160) bit description. . . . . . . . . . . . . 234

Table 221.Flow Control Counter register

(FlowControlCounter - address 0xFFE0 0170) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .235

Table 222.Flow Control Status register (FlowControlStatus -

address 0xFFE0 8174) bit description. . . . . . 235

Table 223.Receive Filter Control register (RxFilterCtrl -

address 0xFFE0 0200) bit description. . . . . . 235

Table 224.Receive Filter WoL Status register

(RxFilterWoLStatus - address 0xFFE0 0204) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .236

Table 225.Receive Filter WoL Clear register

(RxFilterWoLClear - address 0xFFE0 0208) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .237

Table 226.Hash Filter Table LSBs register (HashFilterL -

address 0xFFE0 0210) bit description. . . . . . 237

Table 227.Hash Filter MSBs register (HashFilterH - address

0xFFE0 0214) bit description. . . . . . . . . . . . . 237