NXP Semiconductors UM10237 4.7 UARTn Line Control Register (U0LCR - 0xE000 C00C, U2LCR - 0xE007 800C, U3LCR - 0xE007 C00C)

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 430 o f 792
NXP Semiconductors UM10237
Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter
THRE = 1 and there have not been at least two characters in the UnTHR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UARTn THR FIFO has held two or more characters at one time and
currently, the UnTHR is empty. The THRE interrupt is reset when a Un THR write oc curs or
a read of the UnIIR occurs and the THRE is the highest interrupt (UnIIR[3:1] = 001).
4.6 UARTn FIFO Control Register (U0FCR - 0xE000 C008, U2FCR -
0xE007 8008, U3FCR - 0xE007 C008, Write Only)
The UnFCR controls the operation of the UARTn Rx and TX FIFOs.
4.7 UARTn Line Control Register (U0LCR - 0xE000 C00C, U2LCR -
0xE007 800C, U3LCR - 0xE007 C00C)
The UnLCR determines the format of the data character that is to be transmitted or
received.
Table 385: UARTn FIFO Control Register (U0FCR - address 0xE000 C008,
U2FCR - 0xE007 8008, U3FCR - 0xE007C0 08, Write Only) bit description
Bit Symbol Value Description Reset Value
0 FIFO Enable 0 UARTn FIFOs are disabled. Must not be used in the
application. 0
1 Active high enable for both UARTn Rx and TX
FIFOs and UnFCR[7:1] access. This bit must be set
for proper UARTn operation. Any transition on this
bit will automatically clear the UARTn FIFOs.
1 RX FIFO
Reset 0 No impact on either of UARTn FIFOs. 0
1 Writing a logic 1 to UnFCR[1] will clear all bytes in
UARTn Rx FIFO and reset the pointer logic. This bit
is self-clearing.
2 TX FIFO
Reset 0 No impact on either of UARTn FIFOs. 0
1 Writing a logic 1 to UnFCR[2] will clear all bytes in
UARTn TX FIFO and reset the pointer logic. This bit
is self-clearing.
5:3 - 0 Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
NA
7:6 RX Trigger
Level These two bits determine how many receiver UARTn FIFO characters must be written before an
interrupt is activated.
0
00 Trigger level 0 (1 character or 0x01)
01 Trigger level 1 (4 characters or 0x04)
10 Trigger level 2 (8 characters or 0x08)
11 Trigger level 3 (14 characters or 0x0E)